Method of making increased surface area, storage node electrode, with narrow spaces between polysilicon columns

A method of fabricating a DRAM device, on a semiconductor substrate, comprised of an underlying transistor;

• with a gate insulator, a gate electrode structure, formed from a first silicon oxide, and a first polysilicon layer, insulator sidewall spacers, formed from a second silicon oxide layer, a source and drain region, and an overlying STC structure;
• with a storage node electrode, a dielectric layer, and an overlying plate electrode, and with the upper portion of said storage node electrode, comprised of polysilicon columns, with a narrow space between said polysilicon columns, and extending above a lower portion of said storage node electrode, which is used for contact to said source and drain regions of said underlying transistor, comprising the steps of:
• depositing a third silicon oxide layer on said underlying transistor, of said DRAM device;
• opening a contact hole, in said third silicon oxide layer, to expose top surface of said source and drain regions, of said underlying transistor;
• depositing a second polysilicon layer on top surface of said third silicon oxide layer, and on top surface of said source and drain regions, exposed in said contact hole;
• depositing a silicon nitride layer on said second polysilicon layer;
• opening a first narrow hole, in said silicon nitride layer, exposing a first region, of said second polysilicon layer;
• depositing a fourth silicon oxide layer on said silicon nitride layer, and in said first narrow hole, in said silicon nitride layer;
• anisotropic etching of said fourth silicon oxide layer, to form silicon oxide spacers on the sides of said first narrow hole, creating second narrow hole, smaller in width then said first narrow hole, and exposing a second region of said second polysilicon layer, smaller in width then said first region of said second polysilicon layer;
• anisotropic etching of a top portion of said second region of said polysilicon layer, using said second narrow hole as a mask, to create a trench in top portion of said second polysilicon layer, overlying an unetched, bottom portion of said second polysilicon layer, in said contact hole;
• removal of said silicon nitride layer, exposing top surface of said second polysilicon layer;
• applying a photoresist layer on said top surface of said second polysilicon layer, and on said silicon oxide spacers, while applying a thicker photoresist layer on bottom portion of said second polysilicon layer, exposed in said trench;
• exposure of said photoresist layer overlying said second polysilicon layer, and of said photoresist layer overlying said silicon oxide spacers, while leaving said thicker photoresist layer, in said trench, unexposed;
• removal of exposed said photoresist layer from top surface of said second polysilicon layer, and from said silicon oxide spacers, while leaving a photoresist plug, of unexposed, said thicker photoresist layer, in said trench;
• anisotropic etching of said second polysilicon layer, not covered by said silicon oxide spacers, and not covered by said photoresist plug, in said trench, to create said storage node electrode, comprised of:
• said upper portion of said storage node electrode, with said polysilicon columns, underlying said silicon oxide spacers, with a narrow space between said polysilicon columns, equal in width to said second narrow hole;
• and comprised of said lower portion of said storage node electrode, with said bottom portion of said second polysilicon layer, in said contact hole, underlying said polysilicon columns, contacting said source and drain region of said underlying transistor;
• removal of said photoresist plug, in said trench, of said storage node electrode;
• removal of said silicon oxide spacers, overlying said polysilicon columns, of said storage node electrode;
• forming said dielectric layer on said storage node electrode;
• depositing a third polysilicon layer on said dielectric layer;
• and
• patterning of said third polysilicon layer to form said plate electrode of said STC structure.