Bidirectional parallel data port having multiple data transfer rates, master, and slave operation modes, and selective data transfer termination

An apparatus including a bidirectional parallel signal interface for coupling to and providing a parallel data interface between a computer and a peripheral device external thereto, wherein said computer operates in a plurality of modes including a host mode where data is communicated from said computer to said peripheral device and a slave mode where data is communicated from said peripheral device to said computer, said parallel signal interface comprlsing:

• an interface circuit, including a plurality of resisters, for coupling to a computer and communicating thereto and therefrom a plurality of commands and a first plurality of data, wherein said plurality of registers are for receiving, storing and outputting said plurality of commands;
• a storage circuit, coupled to said interface circuit via a data communications path, for coupling to a peripheral device and communicating directly thereto and therefrom second and third pluralities of data via said data communications path, for storing said first, second and third pluralities of data, and for communicating said first plurality of data directly to and from said interface circuit via said data communications path;
• a host mode controller, coupled to said interface circuit and said storage circuit outside of said data communications path, for receiving a first portion of said plurality of commands outputted by said plurality of registers and in accordance therewith controlling said communication of said second plurality of data from said storage circuit to said peripheral device, and for coupling to said peripheral device and communicating thereto and therefrom a first plurality of control signals;
• and
• a slave mode controller, coupled to said interface circuit and said storage circuit outside of said data communications path, for receiving a second portion of said plurality of commands outputted by said plurality of registers and in accordance therewith controlling said communication of said third plurality of data from said peripheral device to said storage circuit, and for coupling to said peripheral device and communicating thereto and therefrom a second plurality of control signals;
• wherein said communication of said first plurality of control signals by said host mode controller is responsive to a first portion of said first plurality of control signals and said communication of said second plurality of control signals by said slave mode controller is responsive to a second portion of said second plurality of control signals, and wherein said responsiveness of said host mode controller and said responsiveness of said slave mode controller are controllable in accordance with said first and second portions of said plurality of commands, respectively.

An apparatus including a bidirectional parallel signal interface for coupling to and providing a parallel data interface between a computer and a peripheral device external thereto, wherein said computer operates in a plurality of modes including a host mode where data is communicatcd from said computer to said peripheral device and a slave mode where data is communicated from said peripheral device to said cornpater, said parallel signal interface comprising:

• an interface circuit, including a plurality of registers, for coupling to a computer and communicating thereto and therefrom a plurality of commands and a first plurality of data, wherein said plurality of registers are for receiving, storing and outputting said plurality of commands;
• a storage circait, coupled to said interface circuit via a data communications path, for coupling to a peripheral device and communicating directly thereto and therefrom second and third pluralities of data via said data communications path, for storing said first, second and third pluralities of data, and for communicating said first plurality of data directly to and from said interface circuit via said data communications path;
• a host mode controller, coupled to said interface circuit and said storage circuit outside of said data communications path, for receiving a first portion of said plurality of commands outputted by said plurality of registers and in accordance therewith controlling said communication of said second plurality of data from said storage circuit to said peripheral device, and for coupling to said peripheral device and communicating thereto and therefrom a first plurality of control signals;
• and
• a slave mode controller, coupled to said interface circuit and said storage circuit outside of said data communications path, for receiving a second portion of said plurality of commands outputted by said plurality of registers and in accordance therewith controlling said communication of said third plurality of data from said peripheral device to said storage circuit, and for coupling to said peripheral device and communicating thereto and therefrom a second plurality of control signals;
• wherein said communication of said second plurality of data from said storage circuit to said peripheral device is halted by said slave mode controller in accordance with said first portion of said plurality of commands.