US 5,710,932 AGranted

Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism

AssigneeHitachi, Ltd.

InventorsNaoki Hamanaka, Teruo Tanaka

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Abstract

A parallel computer includes a plurality of processor elements (1-1 to 1-n) connected by a network (2); each processor element includes a local memory (6) for holding a program and related data, a processor (3) for performing an instruction in said program, a circuit (5) for transferring data to other processor elements, and a circuit (4) for receiving data sent from another processor element; a memory area (92,8) includes of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and memory (92,8) constructed of a plurality of tag areas, provided for each reception data area, for storing a data tag indicating validity of data in the corresponding reception data area; a transmitting circuit (5) for transmitting data with an attached data identifier predetermined by said data; a circuit for writing the data into one of the plurality of reception data areas in response to data received from the network, and writing valid data tag into one of said plurality of reception data areas, the receiving circuit being parallelly-operated with the processor; and, an access circuit (38) for reading both data and tag from one of the reception data areas determined by the data identifier and from the corresponding tag areas, in response to a data identifier designated by the instruction which is produced from said program for requiring data reception, and for repeatedly reading a tag and data from the tag reception data areas until a valid data tag is read therefrom.

Claims10

Dependent claims

A parallel computer comprising:

(a) a plurality of processor elements connected to each other by a data transfer network;
(b) each of said processor elements including;
(b1) a memory for holding a program and data,
(b2) a processor connected to the memory, executing instructions included in said program, said processor including a memory fetch circuit fetching data required by one of the instructions from said memory and storing data obtained as a result of execution of one of the instructions into said memory,
(b3) a send unit transmitting means connected to the network and said processor transmitting data and address information to a destination processor element via the network, the program being programmed to request the transmitting without receiving a request for transfer of the data from the destination processor element,
(b4) a receive unit connected to the network, receiving therefrom, in parallel to execution of instructions by said processor, data and a data identifier both sent from another processor element,
(b5) a plurality of reception data areas provided within said memory, each reception data area storing data received by said receive unit,
(b6) a plurality of tag areas provided within said memory, each tag area being provided for a corresponding one of the reception data areas, each tag area storing a tag representative of validity of data stored in each corresponding reception data area,
(b7) a write circuit connected to said receive unit and said memory and responsive to receipt of data and a data identifier by said receive unit, writing the received data into one of said plurality of reception data areas determined by the address information received from the network and writing a tag indicative of validity into one of said plurality of tag areas corresponding to said one reception data area, said write circuit operating in parallel to execution of instructions by said processor,
(b8) a memory access circuit included in said processor and connected to said memory, fetching data required by one of the instructions from said memory and storing data obtained as a result of execution of one of the instructions into said memory, said memory access circuit reading a tag held in one of the tag areas corresponding to one of the reception data areas before reading received data from said one of said reception data areas for the program, and
(b9) a check circuit checking if the read tag indicates validity;
wherein said memory access circuit reads data held in said one reception data area to a portion within said processor for processing received data as valid received data under a condition that the checked tag indicates validity, the memory access circuit repeatedly reading a tag held in said one tag area until a tag indicative of validity is read out from the one tag area, in the event that initially the checked tag indicates invalidity.

9 more elements

A method for inter-processor communication of data in a parallel computer which comprises a plurality of processors each of which includes a memory for holding a program to be executed by said each processor and data, wherein said memory includes a group of reception data areas each for holding data received from another processor via the network and a group of tag areas each provided in correspondence to one of the reception data areas and each for holding a tag which indicates whether or not data held in a corresponding reception data area is valid, said tags in all tag areas indicating invalidity before transmitting of data and information, the method comprising the steps executed by each processor element, the steps including:

transmitting to a destination processor element, data and information related to an address of one of the group of reception data areas within said destination processor element into which the data is to be written, the program being programmed so as to request the transmitting without receiving a request from the destination processor element for transmission of the data;
receiving data and information related to an address both transmitted from another processor element, the receiving being done in parallel to execution of instructions of the program by said each processor element;
writing the received data into one of the group of reception data areas, in response to the received address related information;
writing a tag which indicates validity into one of the group of tag areas corresponding to said one reception data area;
checking if a tag held in one of the tag areas indicates validity before reading received data held in one of said groups of reception data areas the one tag region corresponding to the one reception data area;
repeating the checking until the tag indicates validity, in case the tag indicates invalidity initially;
and
supplying data held in said one of the group of reception data areas as valid data for processing to the destination processor, under a condition that the tag has been found as one indicating validity.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/215,262Filed 21 Mar 1994 · continuation
Priority: JP 63-1707029 Jan 1988
Granted: 20 Jan 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification2 codes

G06F 15/17
Interprocessor communication: using an input/output type connection, e.g. channel, I/O port
G06F
Computing and data processing

Family

Serial78,656Parent of this continuation-in-part · filed 28 Jul 1987
Serial145,614Parent of this continuation-in-part · filed 19 Jan 1988
Serial303,626Parent of this continuation · filed 27 Jan 1989
US 5,297,255 AParent of this continuation
US 5,086,498 AParent of this continuation-in-part
US 5,710,932 AThis patent

From the US filing history. Foreign family members aren’t listed.

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