Method and apparatus for enabling a computer system to adjust for latency assumptions

A method for executing a program in a processing system, the program including at least instructions and latency information with which the program was created, the processing system including at least a plurality of processors and dependency checking hardware, said method comprising the steps of:

• (a) issuing from an instruction issue unit instructions of the program, each instruction including at least one operation, and each instruction, except the last instruction of the program, being followed by a next instruction being issued from said instruction issue unit;
• (b) for each operation, processing the operation of the program in one of said processors;
• (c) for each operation, obtaining dependency information by directing the dependency checking hardware to determine if any operation of the next instruction is dependent on the result of the operation;
• and
• (d) when executing said issuing step (a) for said next instruction, stalling said issuing step (a) based on the latency information with which the program was created for the operations being processed in step (b) if the dependency information obtained in step (c) indicates that the next instruction is dependent on the result of the operation.

A processing system for executing a computer program, the computer program including instructions and latency assumption information indicating assumed latencies with which the computer program was created, comprising:

• an instruction issue unit for issuing the instructions of the computer program, each of the instructions including at least one operation;
• a latency storage area connected to said instruction issue unit for receiving and storing the latency assumption information from the computer program;
• one or more processors connected to said instruction issue unit for processing the instructions of the computer program, each of the processors has hardware latency;
• and
• stall determination means for stalling the issuance of the instructions by said instruction issue unit for a cycle based on comparing the latency assumption with which the computer program was created with the hardware latency for a processor of said processors for each of the operations being processed;
• wherein for each instruction in said computer program, said issue unit issues the instruction to a subset of said processors.

A processing system for executing operations of a program, said processing system comprising:

• at least one function pipeline, each function pipeline having a number of stages and an actual pipeline latency;
• a memory area for storing the program, the program including at least the operations and latency assumption information with which the program was created;
• a latency storage area for storing at least one latency assumption for said function pipeline in accordance with the latency assumption information;
• at least one stall circuit, operatively connected to said function pipeline, for determining whether said function pipeline corresponding thereto needs a stall to ensure proper execution and produces a stall signal if a stall is needed;
• a control unit, operatively connected to said function pipeline, said memory area and said latency storage area, for obtaining the latency assumption information from the program and storing the at least one latency assumption for said function pipeline in said latency storage area, for issuing the operations of the program to be executed concurrently in said function pipeline, and for stalling the issuance of the operations when the stall signal requests a stall.