Clock control circuits, systems and methods

A computer system, comprising:

• a microprocessing unit ("MPU");
• and
• a peripheral processing unit ("PPU") external of said MPU that supplies a mask clock signal to said MPU, wherein said MPU comprises:
• a central processing unit (CPU) having a clock input;
• a source of clock pulses;
• a logic circuit having an output to supply a clock control signal wherein said logic circuit is responsive to said mask clock signal, a suspend signal, and a resume signal to generate said clock control signal based on one or more of said mask clock signal, said suspend signal, and said resume signal;
• a clock gate coupled to said clock pulses and having a clock gate output coupled to the clock input of said CPU, said clock gate responsive to said clock control signal to prevent said clock pulses from reaching said central processing unit within one clock cycle of a change in said clock control signal;
• and
• a memory controller having a stop input and a stop acknowledge output, and a third logic circuit responsive to a suspend input to supply a stop signal to said memory controller, and further responsive to said stop acknowledge output from said memory controller to supply a stop oscillator signal to stop at least one clock signal.

A computer system, comprising:

• a microprocessing unit ("MPU");
• and
• a peripheral processing unit ("PPU") external of said MPU that supplies a mask clock signal to said MPU, wherein said MPU comprises:
• a central processing unit (CPU) having a clock input;
• a source of clock pulses compriseing a clock generator having an oscillator and a phase lock loop, said phase lock loop having an output for clock pulses wherein said single-chip MPU has a first terminal for external connection from an output of said oscillator, and a second terminal coupled to an input of said phase lock loop, said output of said oscillator and said input of said phase lock loop being electrically separated on-chip but said first and second terminals being externally buffer-coupled off-chip by a clock buffer unit having an input connected to said first terminal, and outputs including a first output coupled to said second terminal and a second output coupled to said PPU as a clock input thereto, whereby clock skew is reduced;
• a logic circuit having an output to supply a clock control signal wherein said logic circuit is responsive to said mask clock signal, a suspend signai, and a resume signal to generate said clock control signal based on one or more of said mask clock signal, said suspend signal, and said resume signal;
• and
• a clock gate coupled to said clock pulses and having a clock gate output coupled to the clock input of said CPU, said clock gate responsive to said clock control signal to prevent said clock pulses from reaching said central processing unit within one clock cycle of a change in said clock control signal.

A personal computer comprising:

• provision for user input;
• a memory;
• provision for user output;
• and
• an integrated circuit comprising:
• a microprocessor coupled to said provision for user input, said memory, and said provision for user output, said microprocessor comprising a clock control circuit comprising:
• a first logic circuit responsive to a mask clock input, a suspend input and a resume input, and an interrupt override input, to supply a CPU core suspend control signal, wherein, in operation, the frequency of said mask clock input can be varied to stop or slow down the operating speed of a CPU coupled to said CPU core suspend control signal;
• and
• a second logic circuit, responsive to a software controllable enabling input, at least one interrupt input, and a clock signal, to supply said CPU core suspend control signal wherein, in operation, said CPU core suspend control signal can provide a signal to suspend operation of said CPU and can act to lift said signal to suspend when an interrupt is indicated at said interrupt input.