US 5,710,910 A · Asynchronous self-tuning clock domains and method for transferring data among domains

Abstract

One or more domains are independently clocked with separate clocks. Each clock is an asynchronous stop/start clock implementing a self-tuning clocking methodology. Domain circuit speed is monitored and the clock adjusted to tune the domain to run at near maximum speed. Inter-domain data transfers are performed by a four-way handshaking method. In effect the clock period of the respective clocks during the data transfer becomes the slower period of the two domains' clock periods. An inter-domain arbiter is implemented at each domain for deciding which domain's request is to be granted during an immediate clock period. Data input to a domain is tracked to determine when data is present. When no data is present, the domain's clock is stopped.

Claims43

Dependent claims

A method of clocking a domain of register transfer modules, the domain for performing run-time logic operations on input data to generate output data, comprising the steps of:

generating a clock signal for the domain from an adjustable-period-length clock;
repetitively sampling a prescribed register transfer module output signal during a clock period;
detecting a logic-level transition among output signal samples;
determining from when among the samples the output signal transition occurred that the clock period is one of too long, too short, or in tune;
and
either one of adjusting or not adjusting the clock period length automatically in response to the determining step.

3 more elements

A method of independently clocking multiple domains of register transfer modules, the clocking of a given domain of the multiple domains comprising the steps of:

generating a clock signal for the domain from an adjustable-period clock;
repetitively sampling a prescribed register transfer module output signal during a clock period;
detecting a logic-level transition among output signal samples;
determining from when among the samples the output signal transition occurred that the clock period is one of too long, too short, or in tune;
and
either one of adjusting or not adjusting the clock period in response to the determining step;
and
wherein said multiple domains form a system of asynchronous clock domains;
and
wherein the steps of generating, sampling, detecting, determining and adjusting / not adjusting are performed independently for each of the multiple domains;
and
wherein there is an adjustable-period clock for each domain, each adjustable-period clock comprising an asynchronous start/stop clock;
and
Wherein the multiple domains comprise a source domain and a destination domain;
and
further comprising the step of transferring data between the source domain and the destination domain, the transferring step comprising the steps of:
generating at the source domain a request to transfer data to the destination domain;
outputting data from the source domain;
arbitrating at the destination domain among transfer requests from multiple domains;
generating a return grant signal to the source domain after the destination domain arbitration selects the source domain request;
inputting the data at the destination domain;
and
terminating the source domain request in response to the return grant signal.

20 more elements

A self-tuning apparatus, comprising

a first domain of register transfer modules;
a first adjustable-period clock for generating a clock signal for the first domain;
means for sampling a prescribed first domain's register transfer module output signal during a clock period;
means for detecting a logic-level transition among the output signal samples;
means for determining from when among the samples the output signal transition occurred that the clock period is one of too long, too short, or in tune;
means for adjusting the clock period of the first clock in response to the determining step;
a second domain of register transfer modules;
a second adjustable-period clock for generating a clock signal for the first domain;
means for sampling a prescribed second domain's register transfer module output signal during a clock period;
means for detecting a logic-level transition among the second domain output signal samples;
means for determining from when among the samples the second domain output signal transition occurred, that the second clock's clock period is one of too long, too short, or in tune;
means for adjusting the clock period of the second clock in response to the determining step;
means generating at the first domain a request to transfer data to the second domain;
means for outputting data from the first domain;
means for arbitrating at the second domain among transfer requests from multiple domains;
means for generating a return grant signal to the first domain when the destination domain arbitration selects the first domain request;
means for inputting the data at the second domain;
and
means for terminating the first domain request in response to the return grant signal;
and
wherein the first and second domain are part of a system of independently-clocked asynchronous clock domains
wherein the first clock comprises a first asynchronous start/stop clock, and the second clock comprises a second asynchronous start/stop clock.

19 more elements

A method for transferring data among independently-clocked domains forming a system of asynchronous clock domains, each domain comprising a plurality of register transfer modules, a first asynchronous start/stop clock generating a first clock signal for a source domain and a second asynchronous start/stop clock generating a second clock signal for a destination domain, wherein the first clock signal has either one of a shorter or longer clock cycle than the second clock signal while both the first clock signal and second clock signal are transitioning without interruption, the method comprising the steps of:

generating at the source domain a request to transfer data to the destination domain;
outputting first data from the source domain onto a bus linking the source domain and destination domain;
stopping the first clock signal after the source domain request is generated;
arbitrating at the destination domain among transfer requests from multiple domains, wherein the transfer requests include the request from the source domain;
after the destination domain arbitration selects the source domain request, stopping the second clock signal;
after the destination domain arbitration selects the source domain request, generating a return grant signal to the source domain;
terminating the source domain request in response to the return grant signal;
starting the first clock signal after the source domain request is terminated, wherein the first data output by the source domain stays valid on the bus during the ensuing clock cycle of the first clock signal occurring upon starting the first clock signal;
starting the second clock signal after the source domain request is terminated;
upon starting the second clock signal, inputting the data at the destination domain;
and
wherein the steps of stopping the second clock signal and starting the second clock signal result in the second clock signal skipping either one of none or one clock cycle of a second clock signal transitioning without interruption, and wherein the steps of stopping the second clock signal and starting the second clock signal result in the second clock signal skipping not more than one clock cycle of the second clock signal transitioning without interruption.

9 more elements

Dependencies are inferred from the claim text.

Asynchronous self-tuning clock domains and method for transferring data among domains

Life of this patent

Asynchronous self-tuning clock domains and method for transferring data among domains

Life of this patent

Abstract

Claims43