Predictive snooping of cache memory for master-initiated accesses

A method for transferring data between a bus master and a plurality of memory locations at respective addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising the steps of:

• sequentially transferring at least three data units between said bus master and said secondary memory beginning at a first starting memory location address in said secondary memory address space and continuing sequentially beyond an l-byte boundary of said secondary memory address space;
• and
• prior to completion of the transfer of the first data unit beyond said l-byte boundary, determining whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being the line of said secondary memory which includes said first data unit beyond said l-byte boundary,
• all of said transfers of data units in said step of sequentially transferring, occurring at a constant rate.

A method for use with a host processing subsystem, a bus master and memory locations addressable in a secondary memory address space,

• wherein said host processing subsystem includes a CPU and a first cache memory which caches memory locations of said secondary memory address space for said CPU, said first cache memory having a line size of l bytes, said host processing subsystem operating to return, in response to a secondary memory line address specified to said host processing subsystem and the assertion of an inquiry signal to said host processing subsystem, a hit modified indication of whether the specified secondary memory line is cached in a modified state in said first cache memory,
• and wherein said bus master transfers data with said memory locations according to a transaction protocol in which said bus master specifies a starting data unit address for said transaction,
• comprising, in response to initiation of a first transaction and specification by said bus master of a first starting address being the data unit address in the secondary memory address space of a first starting data unit, the steps of:
• specifying to said host processing subsystem, the line address of an N'th l-byte line of said secondary memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said secondary memory address space which includes said first starting data unit,
• after receiving said hit modified indication from said host processing subsystem in response to said inquiry signal, indicating that said N'th l-byte line of said secondary memory address space is cached in a modified state, transferring data units between said bus master and memory locations in said secondary memory address space according to said first transaction;
• and
• after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said host processing subsystem the line address of the N+1'th l-byte line of said secondary memory address space and asserting said inquiry signal a second time.

A method for use with a first processing subsystem, a second processing subsystem and memory locations addressable in a memory address space,

• wherein said first processing subsystem includes a first address-providing unit and a first cache memory which caches memory locations of said memory address space for said first address-providing unit, said first cache memory having a line size of l bytes, said first processing subsystem operating to return, in response to a memory line address specified to said first processing subsystem and the assertion of an inquiry signal (EADS#) to said first processing subsystem, a hit modified indication of whether the specified memory line is cached in a modified state in said first cache memory,
• and wherein said second processing subsystem transfers data with said memory locations according to a transaction protocol in which said second processing subsystem specifies a starting data unit address for said transaction,
• comprising, in response to specification by said second processing subsystem of a first starting address being the data unit address in the memory address space of a first starting data unit, and initiation of a first transaction, the steps of:
• specifying to said first processing subsystem, the line address of an N'th l-byte line of said memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said memory address space which includes said first starting data unit;
• after receiving said hit modified indication from said first processing subsystem in response to said inquiry signal, transferring data units between said second processing subsystem and memory locations in said memory address space according to said first transaction;
• and
• after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said first processing subsystem the line address of the N+1'th l-byte line of said memory address space and asserting said inquiry signal a second time.

Apparatus for transferring data between a bus master and a plurality of memory locations at respective addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising:

• means for sequentially transferring at least three data units between said bus master and said secondary memory beginning at a first starting memory location address in said secondary memory address space and continuing sequentially beyond an l-byte boundary of said secondary memory address space;
• and
• means for, prior to completion of the transfer of the first data unit beyond said l-byte boundary, determining whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being the line of said secondary memory which includes said first data unit beyond said l-byte boundary,
• said means for sequentially transferring, transferring all of said data units at a constant rate.

Apparatus comprising a host processing subsystem, a bus master and memory locations addressable in a secondary memory address space,

• wherein said host processing subsystem includes a CPU and a first cache memory which caches memory locations of said secondary memory address space for said CPU, said first cache memory having a line size of l bytes, said host processing subsystem operating to return, in response to a secondary memory line address specified to said host processing subsystem and the assertion of an inquiry signal to said host processing subsystem, a hit modified indication of whether the specified secondary memory line is cached in a modified state in said first cache memory,
• and wherein said bus master transfers data with said memory locations according to a transaction protocol in which said bus master specifies a starting data unit address for said transaction,
• said apparatus further comprising:
• means for specifying to said host processing subsystem, the line address of an N'th l-byte line of said secondary memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said secondary memory address space which includes a first starting data unit specified by said bus master in initiating a first transaction,
• means for, after receiving said hit modified indication from said host processing subsystem in response to said inquiry signal, indicating that said N+1'th l-byte line of said secondary memory address space is cached in a modified state, transferring data units between said bus master and memory locations in said secondary memory address space according to said first transaction;
• and
• means for, after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said host processing subsystem the line address of the N+1'th l-byte line of said secondary memory address space and asserting said inquiry signal a second time.

Apparatus for use with a first processing subsystem, a second processing subsystem and memory locations addressable in a memory address space,

• wherein said first processing subsystem includes a first address-providing unit and a first cache memory which caches memory locations of said memory address space for said first address-providing unit, said first cache memory having a line size of l bytes, said first processing subsystem operating to return, in response to a memory line address specified to said first processing subsystem and the assertion of an inquiry signal to said first processing subsystem, a hit modified indication of whether the specified memory line is cached in a modified state in said first cache memory,
• and wherein said second processing subsystem transfers data with said memory locations according to a transaction protocol in which said second processing subsystem specifies a starting data unit address for said transaction,
• comprising:
• means for specifying to said first processing subsystem, the line address of an N'th l-byte line of said memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said memory address space which includes a first starting data unit specified by said second processing subsystem in initiating a first transaction;
• means for, after receiving said hit modified indication from said first processing subsystem in response to said inquiry signal, transferring data units between said second processing subsystem and memory locations in said memory address space according to said first transaction;
• and
• means for, after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said first processing subsystem the line address of the N+1'th l-byte line of said memory address space and asserting said inquiry signal a second time.