Cache controller for a non-symetric cache system

A cache memory system, comprising:

• a cache data memory having at least two cache banks of different sizes;
• a cache tag memory organized so as to include tag memories for each of the cache banks of the cache data memory;
• and
• a cache controller coupled to said cache tag memory and said cache data memory and including symmetric match logic and non-symmetric match logic, the symmetric match logic for comparing an address received on a host bus with tag addresses from at first of said tag memories and non-symmetric match logic for comparing the address received on the host bus with tag addresses from a second of said tag memories and a predetermined pattern representing non-cacheable addresses within a cache bank of said cache data memory corresponding to said second tag memory.

A method of generating a cache hit signal in a non-symmetric cache system, comprising the steps of:

• receiving an address on a host bus;
• comparing said address on said host bus to a cache tag address;
• comparing said address on said host bus to a predetermined patterned representing non-cacheable addresses;
• and
• generating a hit signal if said address on said host bus matches said cache tag address and does not match said predetermined pattern.