Loading patent…
AssigneesHitachi, Ltd., Hitachi Computer Engineering Co., Ltd.
InventorsTaiji Horiuchi, Kuniki Toubaru, Hiromichi Kainou
Estimating the term…
A data processing system capable of simultaneously processing a plurality of partial purge requests stored in a purge address stack and of reducing the effective time necessary for carrying out a partial purge process for the partial purging of an address translation lookaside buffer is disclosed. The data processing system comprises a purge address stack (106) having a plurality of registers (106a to 106d) for storing a plurality of partial purge requests, a plurality of comparators (109a to 109d) associated with the registers of the purge address stack respectively and functioning for both gaining normal access to an address translation lookaside buffer and carrying out a partial purge process, and a comparator (110) to be used when an address translator (107) operates. The partial purge process is started when the purge address stack becomes full or when a real address portion determined by the address translator (107) coincides with any one of the real address portions stored in the registers of the purge address stack.
A data processing system provided with an address translator for translating logical addresses into corresponding real addresses and an address translation lookaside buffer for storing a plurality of entries each of an address translation pair of a logical address portion and a real address portion determined by the address translator, comprising a purge address stack for storing a plurality of real addresses to be invalidated for the entries of the address translation lookaside buffer to execute a plurality of cycles of partial purge process for the partial purging of the address translation lookaside buffer collectively for partial purge requests accumulated in the purge address stack.
An address translation lookaside buffer controller in a data processing system which issues a partial purge request with a partial purge requested real address portion to an address translation lookaside buffer which has a plurality of entries each containing a logical address portion and a real address portion as an address translation pair, the system purging address portion pairs in response to a partial purge request which contain the same real address portion with the partial purge request, the controller comprising;
Dependencies are inferred from the claim text.