System and method for asynchronous dual bus conversion using double state machines

In a computer system having a first bus having a first characteristic speed, data width, and protocol, and a second bus having a second characteristic speed, data width, and protocol, wherein at least one of said second characteristics is different than said first characteristics, a method of asynchronous dual bus conversion using first and second pseudo state machines, the method comprising the steps of:

• storing data to be transferred in a data storage means;
• initiating an asynchronous request signal by the first pseudo state machine in communication with a first state machine through the first bus, said first pseudo state machine being a mirror of said first state machine, said asynchronous request signal having a format comprising said first characteristics, thereby requesting that data in the data storage means be transferred;
• and
• initiating an asynchronous reply signal by the second pseudo state machine in communication with a second state machine through the second bus, said asynchronous reply signal having a format comprising said second characteristics, thereby signalling that the data has been sent or is available.

A CPU assembly comprising:

• a microprocessor, said microprocessor being a processor state machine and having a characteristic speed, data width and protocol;
• data storage means associated with said microprocessor;
• a first pseudo state machine mirroring said processor state machine and communicating with said microprocessor and said data storage means;
• and a second pseudo state machine communicating with said first pseudo state machine and coupling said first pseudo state machine to a bus, said bus having a characteristic speed, data width and protocol, at least one said bus characteristic being different than said microprocessor's characteristics, whereby data is transferred between said microprocessor and said bus.