Digital circuitry with improved parallel signature analysis capability

An electronic device, comprising:

• data processing circuitry for performing data processing operations on data provided thereto, said data processing circuitry having a plurality of clock signal paths for carrying respective clock signals;
• and
• a parallel signature analysis circuit including a plurality of latch circuits, each said latch circuit including a data input and a data output, a first said latch circuit having said data output thereof coupled to the data input of a second said latch circuit, and said first latch circuit having said data input thereof coupled to the data output of a third said latch circuit;
• said parallel signature analysis circuit including a predetermined sample node associated with a circuit node driven by said data processing circuitry, sample circuitry which is coupled to said clock signal paths and which can be triggered by any of said clock signals to sample a logic state of said circuit node and to output the sampled logic state on said predetermined sample node regardless of which of said clock signals triggers said sample circuitry, and circuitry for selectively coupling said data input of said first latch circuit to said predetermined sample node.

A circuit for producing a parallel test signature from data obtained from a target circuit, comprising:

• a plurality of latch circuits, each said latch circuit including a data input and a data output, a first said latch circuit having said data output thereof coupled to the data input of a second said latch circuit, and said first latch circuit having said data input thereof coupled to the data output of a third said latch circuit;
• a predetermined sample circuitry with a node of the target circuit;
• sample circuitry which includes a plurality of inputs for receiving respective clock signals from the target circuit and which can be triggered by any of said clock signals to sample a logic state of said node of the target circuit and to output the sampled logic state on said predetermined sample node regardless of which of said clock signals triggers said sample circuitry;
• and
• circuitry for selectively coupling said data input of said first latch circuit to said predetermined sample node.