Frame synchronizing device

A frame synchronizing device for synchronizing a plurality of frames in receiving data being transmitted at a high speed from a broadband digital network, each frame including the first 12 bytes of frame alignment bytes A1 and next 12 bytes of frame alignment bytes A2, said frame synchronizing device comprises:

• a serial/parallel converting means for converting data inputted in serial by a reference clock CLK into parallel data S1 to S8 in the unit of bytes;
• a first comparison means for outputting a first comparison signal X1 by determining whether the parallel data S1 to S8 converted by said serial/parallel converting means correspond to the frame alignment bytes A1;
• a second comparison means for outputting a second comparison signals X2 by determining whether the parallel data S1 to S8 converted by said serial/parallel converter correspond to the frame alignment bytes A2;
• a selection means for selecting one of the two comparison signals X1, X2 outputted from said first and second comparison means, depending on a predetermined selection control signal SELECT;
• a first delay means for producing a first clock CLK1 by delaying an output of said selection means;
• a byte alignment means for aligning the parallel data S1 to S8 outputted from said serial/parallel converting means in accordance with a frame, in response to the first clock CLK1 delayed by said first delay means;
• a divider means for dividing the reference clock CLK by 1/n to output a divided output;
• a second delay means for producing a second clock CLK2 by delaying the divided output of said divider means by a predetermined interval;
• a synchronizing pattern detecting means for detecting whether a first frame synchronizing pattern consisting of subsequent 12 of the frame alignment bytes A1 and a second frame synchronizing pattern consisting of subsequent 12 of the frame alignment bytes A2 are received, in response to any one of the first and second comparison signals outputted from said selection means in synchronism with the second clock CLK2, thereby outputting a frame synchronous pattern detecting signal CNT;
• a pattern continuous identifying means for outputting a frame pulse FP representing whether the first frame synchronizing pattern and, in sequence, the second frame synchronizing pattern are received, in response to the frame synchronous pattern detecting signal CNT representing detection of the first and second frame synchronous patterns in synchronism with the second clock CLK2 produced by said second delay means;
• a synchronizing pattern selecting means for outputting a predetermined selection control signal SELECT so as to effect said selection means to select the second comparison signal X2 and output it, in response to the first frame synchronous pattern detecting signal CNT outputted from said synchronizing pattern detecting means;
• and
• an initializing means for initializing said synchronizing pattern detecting means in response to the frame synchronous pattern detecting signal CNT representing detection of the first and second frame synchronizing patterns, and further initializing said synchronizing pattern detecting means, said pattern continuous identifying means and said synchronizing pattern selecting means in response to the frame pulse FP outputted through said pattern continuous identifying means.