Timing generator for IC testers

A timing generator for IC testers which is provided for each pin of an IC device under test, comprising:

• a memory which stores an integral part of timing set data expressed in terms of a fundamental period, set-side added data obtained by adding a fractional part of said timing set data and data generated at a post-stage of said timing generator for compensating for set-side propagation delay variations, and a reset-side added data obtained by adding said fractional part of said timing set data and data generated at said post-stage of said timing generator for compensating for reset-side propagation delay variations, said memory being read every test cycle;
• coarse timing generating means supplied with said integral part of said timing set data read out of said memory, for generating pulses of a period which is an integral multiple of said fundamental period corresponding to said integral part;
• set-side delay means for delaying the output pulse from said coarse timing generating means by set-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said read-out set-side added data and for delaying the output pulse from said set-side logical delay means by fine delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out set-side added data;
• reset-side delay means for delaying the output pulse from said coarse timing generating means by reset-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said read-out reset-side added data and for delaying the output pulse from said reset-side logical delay means by fine delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out reset-side added data, and
• gate means which permits or inhibits the passage therethrough of the output pulse from said set-side delay means and the output pulse from said reset-side delay means under the control of the set- and reset-side outputs from a waveform generation control circuit.

A timing generator for IC testers which is provided for each pin of an IC device under test, comprising:

• a memory in which integral and fractional parts of timing set data expressed in terms of a fundamental period are stored and from which they are read out every test cycle;
• coarse timing generating means supplied with said integral part of said read-out set data, for generating pulses of a period which is an integral multiple of said fundamental period corresponding to said integral part;
• set-side delay means which adds together, by a set-side adder, said fractional part of said read-out timing set data and set-side propagation delay variation compensating data generated at a post-stage of said timing generator, delays the output pulse from said coarse timing generating means by set-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said added output data, and delays the output pulse from said set-side logical delay means by fine delay means by a time interval corresponding to a fractional part of said added output data;
• reset-side delay means which adds together, by a reset-side adder, said fractional part of said read-out timing set data and reset-side propagation delay variation compensating data generated at said post-stage of said timing generator, delays the output pulse from said coarse timing generating means by reset-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said added output data, and delays the output pulse from said reset-side logical delay means by fine delay means by a time interval corresponding to a fractional part of said added output data;
• and
• gate means which is controlled by set- and reset-side outputs from a waveform generation control circuit to permit or inhibit the passage therethrough of the output pulse from said set-side delay means and the output pulse from said reset-side delay means.