High density two port SRAM cell for low voltage CMOS applications

An electronic memory cell, comprising:

• a latch circuit for storing a data bit;
• a word line and a bit line for providing to the latch circuit the data bit;
• and
• only one transistor connected directly to the word line and directly to ground for controlling a reception of the data bit.

A random access memory, comprising:

• memory cells, each including:
• a latch circuit for storing a datum (0 or 1);
• and
• an input circuit coupled to the latch circuit for receiving the datum, the input circuit including first, second, and third switching devices, the first and second switching devices coupled in parallel both to the latch circuit and to the third switching device, the third switching device coupled directly to ground;
• write bit lines and write word lines for selectively transmitting data to the memory cells;
• and
• the first and second switching devices each coupled to a separate one of the write bit lines, the third switching device further coupled directly to a write word line.

An apparatus, comprising:

• a plurality of memory cells each including latch means for storing a data bit;
• receiving means coupled to each of the memory cells for transmitting data bits to be stored in selected ones of the memory cells, the receiving means comprising write bit lines and a write word line;
• the memory cells each further including:
• input means coupled to the receiving means for transmitting the data bit to the latch means, the input means including an input transistor coupled to the receiving means and to ground;
• and
• control means for controlling data bit storage, the control means including a pair of AND gates each coupled to a separate one of a pair of said write bit lines, the pair of write bit lines both coupled to a portion of the plurality of memory cells.

An apparatus, comprising:

• a plurality of memory cells each including latch means for storing a data bit;
• receiving means coupled to each of the memory cells for transmitting data bits to be stored in selected ones of the memory cells, the receiving means comprising write bit lines and a write word line;
• and
• the memory cells each further including:
• input means, for transmitting the data bit from the receiving means to the latch means, having an input transistor coupled to the receiving means and directly to ground, and a pair of transistors coupled in parallel both to the input transistor and to the latch means, and the pair of transistors each further coupled directly to a separate write bit line.