Low power dynamic random access memory

A low power dynamic random access memory having a plurality of memory cells therein, said random access memory comprising:

• a first field effect transistor connected to a pair of bitlines for allowing electric charge of the bitline having higher voltage to flow to the bitline having lower voltage, said first field effect transistor being activated by a first precharge control signal;
• a plurality of even number of serially coupled inverters for generating a second precharge control signal from the first precharge control signal;
• a precharge control circuit comprising a second field effect transistor and a third field effect transistor connected to the pair of bitlines and to a constant voltage source for setting the voltages on the bitlines to the voltage of the constant voltage source in response to the second precharge control signal;
• and
• a sense amplifier connected to the pair of bitlines for amplifying the voltages on the bitlines.