US 5,710,737 AGranted

Semiconductor memory device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsYuichiro Komiya, Kiyohiro Furutani, Tsukasa Ooishi, Kei Hamade

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Abstract

A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.

Claims10

Dependent claims

A semiconductor memory device, comprising:

input means for supplying a first bit line with a first signal of a first potential which is the equivalent of a potential of input data and supplying a second bit line with a second signal of a second potential which is the reverse of said potential of said input data;
a first memory cell provided on an intersection of said first bit line and a word line of a first type which is a word line assigned either odd number or even number;
and
a second memory cell provided on an intersection of said second bit line and a word line of a second type opposite to said first type, wherein
said first signal is written into said first memory cell when said first bit line and said word line of said first type are selected and said second signal is written into said second memory cell when said second bit line and said word line of said second type are selected,
said semiconductor memory device further comprising:
burn-in mode signal output means for outputting a burn-in mode signal which is brought into an active state when a burn-in test is performed;
and
input data inverting means provided in an ante-stage of said input means to receive said burn-in mode signal, for automatically inverting said input data when said word line of said second type is selected while said burn-in mode signal is active.

6 more elements

A semiconductor memory device, comprising:

burn-in mode signal output means for outputting a burn-in mode signal which is brought into an active state in response to a column address strobe signal, a row address strobe signal, a write enable signal and a plurality of address signals inputted from a plurality of address terminals, all of which are supplied at a prescribed timing during a burn-in test, and a source voltage of higher level than a level of a normal high-potential signal which is applied to specific address terminal different from said plurality of address terminals;
and
burn-in mode verifying means provided between said specific address terminal and a ground potential, for verifying if said semiconductor memory device enters a burn-in mode and carrying a leak current between said specific address terminal and said ground potential in response to said burn-in mode signal at said active state.

Dependencies are inferred from the claim text.