Combined adder and decoder digital circuit

A combined adder/decoder circuit which combines the functions of addition and decoding, comprising:

• a first decoder logic circuit for decoding a group of N binary bits of a first operand to a first one-out-of-2N output;
• a second decoder logic circuit for decoding a group of N binary bits of a second operand to a second one-out-of-2N output;
• and
• a shifter logic circuit for receiving said first one-out-of-2N output and shifting an active bit position of said first one-out-of-2N output left by a number of positions according to said second one-out-of-2N output thereby generating a decoded and summed one-out-of-2N output of said first and second operands, wherein said first and second operands are divided into several subgroups of a few adjacent bits and said first and second decoder logic circuits and said shifter logic circuit are divided into a tree-based decoder in which subgroups are decoded and added in a merged shifting and decoding operation, subgroups are divided from most significant bits to least significant bits and the shifter logic circuit of each subgroup, except for the most significant bits subgroup, is extended so that circular shifting does not occur in the event of a carry within in the subgroup, decoded and added subgroups are combined to generate said decoded and summed output of said first and second operands.