Filtering method and digital over sampler filter with a finite impulse response having a simplified control unit

A digital filter designed to receive at an input a flow of input samples and generate at an output a flow of oversampled output samples, said digital filter comprising:

• a) first memory means designed to memorize a sequence of 2 N filtering coefficients having a data output and a first control input,
• b) second memory means designed to memorize at least 2 M consecutive samples of said input flow, M being less than N, having a data input connected to said input of said filter and having a data output and a second control input,
• c) a multiplier having data inputs connected to the data outputs of said memory means and having a data output,
• d) an accumulator having a data input connected to the data output or said multiplier and a data output connected to said output of said filter and designed to add the content of itself with the value present at the data input and present at the data output the result of said sum, and
• e) a control unit comprising addressing means connected to said control inputs;
• wherein said addressing means comprise a first counter modulus 2 N receiving at input a clock signal generating at output a first word made up of N bits and are designed to supply said first word to said first control input and wherein said filtering coefficients are memorized in said first memory means;
• wherein said addressing means comprise additionally a second counter modulus 2 M receiving at input said clock signal generating at output a fifth word made up of M bits and are designed to supply said fifth word to said second control input and in which said control unit comprises also block means designed to generate a block signal, which is active for the duration of a semi-period of said clock signal, every 2 N periods of said clock signal and supply it to a write enablement input of said second memory means at a reset input of said first counter and a block input of said second counter.

A filtering circuit, comprising:

• a first counter which is modulo 2N and which is operatively connected to be clocked by a clock signal and operatively connected to provide addresses to a coefficient memory;
• a second counter which is modulo 2M, where M is less than N, and which is operatively connected to be clocked by said clock signal and operatively connected to control the output of a data memory which is connected to receive an incoming sequence of data;
• a third counter which is interconnected with additional logic to generate an output pulse once in 2N cycles of said clock signal, said output pulse being connected to reset said first counter and to activate said second counter;
• and
• multiply and accumulate logic connected to multiply data from said data memory with coefficients from said coefficient memory and provide a filtered output from summed partial products thereof
• wherein said first counter is connected through a translation circuit which interchanges M-N more significant bits with N less significant bits to provide retrieval of coefficients in a predetermined sequence.

A filtering method, comprising the non-sequential steps of:

• clocking a first counter which is modulo 2N with a clock signal;
• clocking a second counter which is modulo 2M, where M is less than N, with said clock signal;
• clocking a third counter to generate an output pulse therefrom once in 2N cycles of said clock signal;
• applying said output pulse to reset said first counter and to activate said second counter;
• providing addresses to a coefficient memory in dependence on outputs of said first counter;
• applying an output of said third counter as a control signal to control the output of a data memory which is connected to receive an incoming sequence of data;
• and
• multiplying data from said data memory with coefficients from said coefficient memory, and accumulating products therefrom, to provide a filtered output signal;
• wherein said first counter is connected through a translation circuit which interchanges M-N more significant bits with N less significant bits to provide retrieval of coefficients in a predetermined sequence.