Internal postage meter machine interface circuit

An internal postage meter machine interface circuit comprising transmission and reception registers for storing data transmitted in parallel and a shift register for the parallel-to-serial conversion of the transmitted data, a state machine in a print data controller having an input side supplied with an encoder signal and with DMA control signals and a signal from a mode register identifying a predetermined operating mode for said print data controller, the state machine controlling the shift register, and a test circuit controlled by said state machine for, in cooperation with a control unit, setting an operating mode of the print data controller, said test circuit comprising means for checking the operating mode of said print data controller for conformity with said predetermined operating mode.

An internal postage meter machine interface circuit comprising transmission and reception registers for storing data transmitted in parallel and a shift register for serial-to-parallel and parallel-to-serial conversion of the transmitted data, a print data controller having a state machine having an input side connected to a mode register group for setting an operating mode of said print data controller and having an output side connected to control inputs of the transmission shift register, a test circuit and a print register for inserting an acknowledgement code emitted by a code generator into a test shift register in said test circuit controlled by said state machine, said acknowledgement code being stored in said test shift register so as to be fetchable in parallel, and said test circuit being operable in a security printer mode for monitoring serial data transfer between said print register and printer head electronics, and the transmission shift register, and a watchdog circuit means for monitoring the received bits for a predetermined status change for, if necessary, triggering an interrupt to the control unit and a print data command to the printer head.