Scaled video output overlaid onto a computer graphics output

A display control apparatus, storing video digital pixel data, for generating a video output having a scale factor value of N/D with respect to the video digital pixel data, comprising:

• a timing generator, adapted to receive a horizontal synchronization signal of a computer graphics output and a pixel number of horizontal scan line of the video output, for generating a pixel clock of the video output;
• a frame buffer for storing the video digital pixel data, responsive to the pixel clock of the video output, for generating the video output in synchronization with the computer graphics output, wherein the timing generator is a phase lock loop which generates the pixel clock of the video output, the timing generator comprises:
• a programmable frequency divider, coupled to a controller bus for receiving the pixel number, having an input receiving the pixel clock of the video output and an output generating a horizontal lock signal;
• a phase detector for generating a control signal by comparing phase difference between the horizontal synchronization signal and the horizontal lock signal;
• a loop filter for generating a filtered control signal by filtering out a noise within the control signal;
• and
• a voltage controlled oscillator, in response to the filtered control signal, for generating the pixel clock of video output.

A display control apparatus for overlaying a video output onto a computer graphics output, comprising:

• image overlay control means, coupled to a controller bus and receiving a first analog pixel data of the computer graphics output and, responsive to a pixel clock of the video output, a horizontal lock signal, and a vertical synchronization signal of the computer graphics output, for generating an overlay key signal;
• and
• a multiplexer, adapted to receive the first analog pixel data of the computer graphics output and a second analog pixel data of the video output, and, responsive to the overlay key signal, for outputting the first and second analog pixel data selectively, wherein the image overlay control means comprises:
• a first control means for generating a color key signal;
• a second control means for generating a window key signal;
• and
• an AND gate, adapted to receive the color key signal and the window key signal, for generating the overlay key signal.

A display control apparatus storing video digital pixel data, for generating scaled video data which has a scale factor value of N/D with respect to the video digital pixel data, comprising:

• control means, responsive to a scale control signal, for generating an address increment signal which corresponds to the scale factor value of N/D, the scale control signal being one of a normal signal, a scale-down signal and a scale-up signal;
• output address pointer means, responsive to the address increment signal, an address adjustment signal and a pixel clock of the scaled video data, for generating an output address, the address adjustment signal is enabled each time an accumulated truncation error, caused by the scale factor value of N/D, is greater than a criterion value;
• a dual port memory, storing the video digital pixel data and, responsive to the output address, for generating the scaled video data;
• and
• a digital to analog converter for converting the scaled video data into video analog pixel data, wherein the control means comprises:
• a control register, coupled to a controller bus, for selectively generating the scale control signal;
• an address increment register, coupled to the controller bus, for generating the address increment signal;
• a criterion register, coupled to the controller bus, for storing the criterion value;
• and
• a remain addend register coupled to the controller bus, the remain addend register has a first input receiving the scale-down signal and a second input receiving the address adjustment signal.

A display control apparatus, storing video digital pixel data, for generating a scaled video output which has a scale factor value of N/D with respect to the video digital pixel data, overlaid onto a computer graphics output comprising:

• a timing generator, adapted to receive a horizontal synchronization signal of the computer graphics output and a pixel number of horizontal scan line of the scaled video output, for generating a pixel clock of the scaled video output and a horizontal lock signal;
• a scaling buffer, responsive to the pixel clock of the scaled video output, for generating the scaled video output;
• and
• an overlay control means, coupled to a controller bus, receiving analog pixel data of the computer graphics output and responsive to the pixel clock of the scaled video output, the horizontal lock signal and a vertical synchronization signal of the computer graphics output, for overlaying the scaled video output onto the computer graphics output, wherein the timing generator comprises:
• a programmable frequency divider, coupled to the controller bus for receiving the pixel number, having an input receiving the pixel clock of the scaled video output and an output generating the horizontal lock signal;
• a phase detector for generating a control signal by comparing phase difference between the horizontal synchronization signal and the horizontal lock signal;
• a loop filter for generating a altered control signal by filtering out a noise within the control signal;
• and
• a voltage controlled oscillator for generating the pixel clock of the scaled video output, in response to the filtered control signal.