Input logic signal buffer circuits

An input logic signal buffer circuit comprising:

• a current source;
• first and second field effect transistors, serially electrically connected between said current source and a first reference voltage, said first field effect transistor having a gate which is electrically connected to a second reference voltage;
• third and fourth field effect transistors, serially electrically connected between said current source and said first reference voltage, to define an output node therebetween, said third field effect transistor having a gate which is electrically connected to an input logic signal, wherein said first, second, third and fourth field effect transistors are electrically interconnected to form a differential amplifier which differentially amplifies said second reference voltage and said input logic signal at said output node;
• and
• a fifth field effect transistor, the gate of which is electrically connected to said input logic signal, and wherein one of the drain and source of the fifth field effect transistor is electrically connected to said output node.

An input logic signal buffer circuit comprising:

• a first field effect transistor, the source and drain of which are serially electrically connected between a first reference voltage and a first node;
• second and third complementary field effect transistors, the sources and drains of which are serially electrically connected between said first node and a second reference voltage to define a second node therebetween, wherein the gate of said second field effect transistor is electrically connected to a third reference voltage;
• fourth and fifth complementary field effect transistors, the sources and drains of which are serially electrically connected between said first node and said second reference voltage to define a third node therebetween, wherein the gate of said fourth field effect transistor is electrically connected to an input logic signal, and wherein the gates of said third and fifth field effect transistors are electrically connected to said second node;
• and
• a sixth field effect transistor and a current limiter serially connected between said third node and said second reference voltage, wherein the gate of said sixth field effect transistor is electrically connected to said input logic signal.