Lateral MOSFET with modified field plates and damage areas

A field effect transistor comprising:

• a substrate formed from a silicon carbide material system and including a first conductivity type area;
• a channel layer positioned on the first conductivity type area of the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;
• a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;
• a source terminal positioned in electrical contact with the channel layer, the source terminal including a source contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the source contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the source terminal further including a source contact on the surface of the channel layer and in electrical contact with the source contact region;
• a drain terminal positioned in electrical contact with the drift region, the drain terminal including a drain contact region having the second conductivity type and the third doping concentration, the drain contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the drain terminal further including a drain contact on the surface of the channel layer and in electrical contact with the drain contact region, the source contact region and the drain contact region defining a current channel therebetween including the channel region and a portion of the drift region;
• the current channel extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion, and the current channel having a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion;
• an oxide layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the drain contact;
• a gate terminal including a gate contact positioned on a surface of the first portion of the oxide layer overlying a portion of the channel region in the current channel;
• the drain contact having a first field plate electrically attached to the drain contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the gate terminal;
• and
• a damaged region defined in the drift region and underlying the edges of the first field plate and the gate contact in the curved transistor portion to reduce electric fields at the edges of the first field plate and the gate contact.

A field effect transistor comprising:

• a substrate formed from a silicon carbide material system and including a first conductivity type area;
• a channel layer positioned on the first conductivity type area of the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;
• a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;
• a source terminal positioned in electrical contact with the channel layer, the source terminal including a source contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the source contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the source terminal further including a source contact on the surface of the channel layer and in electrical contact with the source contact region;
• a drain terminal positioned in electrical contact with the drift region, the drain terminal including a drain contact region having the second conductivity type and the third doping concentration, the drain contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the drain terminal further including a drain contact on the surface of the channel layer and in electrical contact with the drain contact region, the source contact region and the drain contact region defining a current channel therebetween including the channel region and a portion of the drift region;
• the current channel extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion, and the current channel having a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion;
• an oxide layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the drain contact;
• a gate terminal including a gate contact positioned on a surface of the first portion of the oxide layer overlying a portion of the channel region in the current channel;
• the drain contact having a first field plate electrically attached to the drain contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the gate terminal;
• the gate contact having a second field plate electrically attached to the gate contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the drain terminal, and the edge of the second field plate being spaced from the edge of the first field plate a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion;
• and
• a damaged region defined in the drift region and underlying the edges of the first and second field plates.

A field effect transistor comprising:

• a substrate formed from a silicon carbide material system and including a first conductivity type area;
• a channel layer positioned on the first conductivity type area of the substrate and defining a surface, the channel layer having a second conductivity type and a first doping concentration;
• a laterally extending drift region defined in the channel layer, the drift region having the second conductivity type and a second doping concentration higher than the first doping concentration;
• a source terminal positioned in electrical contact with the channel layer, the source terminal including a source contact region having the second conductivity type and a third doping concentration greater than the second doping concentration, the source contact region being defined in the channel layer adjacent the surface thereof and spaced from the drift region so as to define a channel region in the channel layer, the source terminal further including a source contact on the surface of the channel layer and in electrical contact with the source contact region;
• a drain terminal positioned in electrical contact with the drift region, the drain terminal including a drain contact region having the second conductivity type and the third doping concentration, the drain contact region being defined in the channel layer adjacent the surface thereof and adjacent the drift region, the drain terminal further including a drain contact on the surface of the channel layer and in electrical contact with the drain contact region, the source contact region and the drain contact region defining a current channel therebetween including the channel region and a portion of the drift region;
• the current channel extending laterally, generally parallel with the surface of the channel layer and defining a straight transistor portion and a curved transistor portion, and the current channel having a first length in the straight transistor portion and a second length, greater than the first length, in the curved transistor portion;
• an oxide layer positioned on the channel layer and including a first portion with a first thickness overlying the channel region and a second portion with a second thickness greater than the first thickness overlying the drift region, the second portion extending laterally from the first portion to adjacent the drain contact;
• a gate terminal including a gate contact positioned on a surface of the first portion of the oxide layer overlying a portion of the channel region in the current channel;
• the drain contact having a first field plate electrically attached to the drain contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the gate terminal;
• the gate contact having a second field plate electrically attached to the gate contact and positioned on the second portion of the oxide layer so as to define an edge extending toward the drain terminal, and the edge of the second field plate being spaced from the edge of the first field plate a first distance in the straight transistor portion and a second distance, greater than the first distance, in the curved transistor portion;
• and
• a damaged region defined in the drift region and underlying the edges of the first and second field plates only in the curved transistor portion to reduce electric fields at the edges of the first field plate and the third metal contact.