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US 5,710,453 AGranted
Transistor structure and method for making same
AssigneeSGS-Thomson Microelectronics S.A.
InventorFrank Randolph Bryant
Life of this patent
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Abstract
A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.
Claims13
An integrated circuit device comprising:
- a substrate;
- a gate structure, wherein the gate structure includes:
- a gate oxide layer on the substrate, the gate oxide layer having a region thicker than a surrounding portion of the gate oxide layer;
- a nitride layer on the gate oxide layer, the nitride layer approximately coextensive with the thicker region of the gate oxide layer;
- a polysilicon layer over the nitride layer;
- a channel region under the gate structure;
- and
- source/drain regions in the substrate adjacent the channel region.
5 more elements
An integrated circuit device comprising:
- a substrate;
- a gate structure, wherein the gate structure includes:
- a gate oxide layer on the substrate,
- a nitride layer on the gate oxide layer, and
- a polysilicon layer over the nitride layer;
- a channel region under the gate structure;
- and
- source/drain regions in the substrate adjacent the channel region wherein the gate has a peripheral edge and further including an uplift in the nitride layer occurring in portions of the nitride layer proximate the peripheral edge of the gate structure, the uplift caused by reoxidation of the gate structure, wherein asperities are absent from the polysilicon layer.
5 more elements
An integrated circuit device comprising:
- a substrate;
- a gate structure, wherein the gate structure includes a gate oxide on the substrate, a nitride layer on the gate oxide layer, and a polysilicon layer over the nitride layer, wherein the gate structure includes a peripheral edge;
- a channel region under the gate structure, wherein the channel region is defined by the peripheral edge of the gate structure;
- and
- source/drain regions in the substrate adjacent the channel region.
2 more elements
Dependencies are inferred from the claim text.