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US 5,710,443 AGranted
Merged device with aligned trench fet and buried emitter patterns
AssigneeSGS-Thompson Microelectronics S.A.
InventorRichard A. Blanchard
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Abstract
A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.
Claims16
A switched-emitter merged device structure, comprising:
- a plurality of field-effect control transistor portions each comprising a source region of a first conductivity type near a first surface of a substantially monocrystalline semiconductor material, and a gate connected to control the flow of carriers of said first conductivity type from said source region through a channel region downwardly into said semiconductor material;
- and
- a plurality of power bipolar transistor portions each comprising an emitter diffusion of said first conductivity type overlying a portion of a single base diffusion of a second conductivity type;
- wherein said emitter diffusion include a first buried layer having multiple separate spaced apart minimum-geometry emitter diffusion portions on the order of a respective control transistor portion, and said single base diffusion a second buried layer which extends between and connects with adjacent emitter diffusion portions of said first buried layer;
- and
- wherein individual ones of said emitter diffusions of said bipolar transistor portions are aligned to respective corresponding ones of said control transistor portions for providing an increased emitter diffusion length per unit area such that a current density of said plurality of power bipolar transistor portions is maximized.
3 more elements
A switched-emitter merged device structure, comprising:
- a plurality of field-effect trench transistor portions each comprising a source region of a first conductivity type near a first surface of a substantially monocrystalline semiconductor material, and an insulated gate connected to control the flow of carriers of said first conductivity type from said source region through a second-conductivity-type channel region along the wall of a trench downwardly into said semiconductor material;
- and
- a plurality of power bipolar transistor potions each comprising an emitter diffusion of said first conductivity type overlying a portion of a single base diffusion of a second conductivity type;
- wherein said emitter diffusions include a first buried layer having multiple separate spaced apart minimum-geometry emitter diffusion portions on the order of a respective trench transistor portion, and said single base diffusion includes a second buried layer which extends between and connects with adjacent emitter diffusion portions of said first buried layer;
- and wherein said emitter diffusions are aligned in a pattern which predominantly corresponds to the pattern of said trenches for providing an increased emitter diffusion length per unit area such that a current density of said plurality of power bipolar transistor portions is maximized.
2 more elements
Dependencies are inferred from the claim text.