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US 5,710,442 AGranted
Semiconductor device and method of manufacturing same
AssigneeHitachi, Ltd.
InventorsAtsuo Watanabe, Katsuaki Saito
Life of this patent
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Abstract
A semiconductor device sets an impurity density of a p base layer in a bevel end-face region to a density lower than that in an operating region and has a parasitic channel preventive region provided between the bevel end-face region and the operating region. Since the blocking-voltage and the current-carrying capacity can be adjusted independently from each other, the blocking voltage and the current-carrying capacity can be both improved.
Claims12
A semiconductor device comprising:
- a semiconductor base substrate having a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer located on the first semiconductor layer, a first conductivity type third semiconductor layer located on the second semiconductor layer and a second conductivity type fourth semiconductor layer located on the third semiconductor layer, the semiconductor base substrate including a first region adjacent to an end of said semiconductor base substrate and a second region provided inside the first region;
- a first main electrode provided on the first semiconductor layer;
- and
- a second main electrode provided on the fourth semiconductor layer,
- said third semiconductor layer in the first region having an average impurity density smaller than that of the third semiconductor layer in the second region, and
- said second main electrode being in contact with the third semiconductor layer between the first and second regions,
- wherein a parasitic channel preventive region is provided between the first and second regions, the parasitic channel preventive region having a width greater than or equal to a diffusion length of a minority carrier in the second semiconductor layer.
4 more elements
A semiconductor device comprising:
- a semiconductor base substrate having a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer located on the first semiconductor layer, a first semiconductor type third semiconductor layer located on the second semiconductor layer and a second conductivity type fourth semiconductor layer located on the third semiconductor layer, the semiconductor base substrate including a first region adjacent to an end of said semiconductor base substrate and a second region provided inside the first region;
- a first main electrode provided on the first semiconductor layer;
- and
- a second main electrode provided on the fourth semiconductor layer,
- said third semiconductor layer in the first region having an average impurity density smaller than that of the third semiconductor layer in the second region, and
- said second main electrode being in contact with the third semiconductor layer between the first and second regions,
- wherein a parasitic channel preventive region is provided between the first and second regions, and
- wherein a first conductivity type fifth semiconductor layer having an impurity density higher than that of the first region is provided on the surface of the third semiconductor layer in the parasitic channel preventive region.
5 more elements
Dependencies are inferred from the claim text.