Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock

A multiprocessor system comprising:

• a time division multiplexed bus for transferring digital data at intervals determined by a clock signal, and
• a plurality of processing nodes operatively connected to each other with said bus to form a synchronous network, each of said processing nodes including a digital signal processing element, a read/write dual port memory element and a dual port memory control element;
• wherein each said dual port memory control element further includes means for selecting the total number of said plurality of processing nodes;
• wherein said means for selecting determines that said total number of processing nodes is any integral power of 2;
• wherein each said dual port memory element has a first port for exchanging data with a corresponding digital signal processing element of the same processing node according to the phase of said clock signal, and a second port controlled by a dual port memory control element of the same processing node for exchanging data between said dual port memory element and said bus according to the phase of said clock signal;
• and
• wherein each said dual port memory includes a plurality of address locations which are accessible to said digital signal processing element only during a first phase of said clock signal and which are accessible to said bus only during a second, opposite phase of said clock signal, whereby conflicts between each said digital signal processing element and said bus are avoided.