Processor architecture providing speculative, out of order execution of instructions

A processor for processing information in response to an ordered sequence of instructions, the ordered sequence of instructions including a plurality of arithmetic instructions that control arithmetic operations on the information, said processor being capable of performing speculative, out-of-order execution of instructions contained within said ordered sequence of instructions for enhanced computational efficiency, said processor comprising:

• a register array comprising a plurality of registers, each register having a unique register number;
• an instruction fetcher for fetching the speculative sequence of instructions from an instruction memory;
• an instruction shelver coupled to said instruction fetcher for receiving fetched instructions and for storing multiple such instructions in the order fetched, said shelving means comprising:
• an operation code field for storing an operation code associated with each of said instructions;
• an associatively addressable destination register field for storing a destination register number associated with each of said instructions;
• a result field for storing a result associated with each of said instructions;
• an instruction scheduler coupled to said instruction shelver for continuously selecting instructions in said instruction shelver for which all information required for execution is available in said register array or said instruction shelver and for issuing those instructions for execution in an order independent of the order in which those instructions were fetched;
• a first arithmetic unit coupled to said instruction scheduler for performing operations on information in one of said register array or said instruction shelver in response to operation codes associated with instructions supplied from said instruction shelver to generate execution results, said first arithmetic unit further coupled to said instruction shelver so that said instruction shelver receives the execution result and is capable of storing the execution result in said result field;
• a second arithmetic unit coupled to said instruction scheduler for performing operations on information in one of said register array or said instruction shelver in response to operation codes associated with instructions supplied from said instruction shelver to generate execution results, said second arithmetic unit further coupled to said instruction shelver so that said instruction shelver receives the execution results and is capable of storing the execution results in said result field, wherein said instruction scheduler is capable of simultaneously supplying said first arithmetic unit and said second arithmetic unit with different operation codes corresponding to arithmetic instructions from said instruction shelver, along with the information needed to execute each of said different arithmetic instructions stored in either said register array or said instruction shelver;
• a retirement unit for retiring the results of execution of the oldest instruction in said instruction shelver into said register array and removing that instruction from said instruction shelver.