Method and apparatus for providing bus protocol simulation

A method for transferring data in a multi-processor data processing system having a first processor, a second processor, and an interface circuit, the interface circuit having a memory, the method comprising the steps of:

• storing a first value in the memory, the first value having a control portion and having a data portion;
• storing a second value in the memory, the second value having a control portion and having a data portion;
• storing a third value in the memory, the third value having a control portion and having a data portion;
• accessing the first value in the memory;
• if the control portion of the first value has a predetermined state, providing a first data valid control signal from the interface circuit to the first processor during a first bus cycle;
• accessing the second value in the memory;
• if the control portion of the first value has the predetermined state, providing the data portion of the second value to the first processor during a second bus cycle;
• if the control portion of the second value has the predetermined state, providing the first data valid control signal from the interface circuit to the first processor during the second bus cycle;
• accessing the third value in the memory;
• and
• if the control portion of the second value has the predetermined state, providing the data portion of the third value to the first processor during a third bus cycle.

A data processing system, comprising:

• a data bus;
• an address bus for providing a first address and for providing a second address;
• a control bus;
• a plurality of processors;
• and
• a storage circuit, coupled to said data bus, said address bus, and said plurality of processors;
• wherein said storage circuit comprises:
• first memory means, accessed by the first address, for storing a control portion of a first value;
• second memory means, accessed by the first address, for storing a data portion of the first value;
• third memory means, accessed by the second address, for storing a control portion of a second value;
• and
• fourth memory means, accessed by the second address, for storing a data portion of the second value;
• wherein said data processing system further comprises:
• control means for receiving the control portion of the first value, in response to the control portion of the first value having a predetermined value said control means providing a control signal to a first one of said plurality of processors to initiate transfer of the data portion of the second value to the first one of the plurality of processors, said control means being coupled to said control bus, to said storage circuit, and to the first one of the plurality of processors.