Method and apparatus for register renaming in a computer system using a separate arithmetic available queue

A method for register renaming in a computer system comprising the steps of:

• storing physical register addresses corresponding to t architected register addresses in a map table;
• storing addresses of physical register available for arithmetic in an arithmetic available queue, said arithmetic available queue connected to a first input of said map table and connected to a first output from said map table;
• storing addresses of physical register available for loads in a load available queue, said load available queue connected to a second input of said map table;
• storing a plurality of pending physical store addresses in a store queue, said store queue including an arithmetic store return queue connected to said first output from said map table and connected to a second input of said arithmetic available queue, and a load store return queue coupled between said map table and said load available queue;
• comparing a displaced physical register address with said plurality of store addresses for updating said arithmetic available queue;
• comparing a freed physical register address with said plurality of store addresses for updating said load available queue;
• storing a plurality of pending source and target instruction addresses in an instruction queue;
• and comparing one of said plurality of pending store addresses with said source and target instruction addresses in said instruction queue for updating said load available queue and said arithmetic available queue;
• directly moving said displaced physical register address from said map table to said arithmetic available queue responsive to no matching store address to said displaced address being identified;
• and
• storing said displaced physical register address from said map table in an arithmetic store return queue responsive to a matching store address to said displaced address being identified.