US 5,708,817 A · Programmable delay of an interrupt

Abstract

A programmable interrupt delay in a communication circuit enables accurate timing of an interrupt delay without tying up processor CPU cycles in the execution of a delay loop. The interrupt delay comprises a memory containing the program delay value. A communication circuit which generates an interrupt output corresponding to the transmission of a communication data stream is coupled to a timing circuit having a time value. This timing circuit also has a timing start input, which triggers timing of the timing value upon receipt of the interrupt output. A comparator coupled to the memory and to the timing circuit compares the time value to the delay value and generates a delayed interrupt when the time value and the delay value are equal.

Claims17

Dependent claims

A programmable interrupt delay comprising:

a memory containing at least one delay value;
a communication circuit which generates an interrupt output corresponding to the communication of a data stream;
a timing circuit having an input coupled to the communication circuit and having an output, and which begins generating and incrementing a timing value in response to the generation of said interrupt output;
and
a comparator coupled to the memory and to the output of the timing circuit for comparing one of the at least one delay values to the timing value and generating a delayed interrupt responsive to the comparison.

2 more elements

Dependencies are inferred from the claim text.

Programmable delay of an interrupt

Life of this patent

Programmable delay of an interrupt

Life of this patent

Abstract

Claims17