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US 5,708,816 AGranted
Method and apparatus for interrupt management for low power PDA
AssigneeApple Computer, Inc.
InventorMichael F. Culbert
Life of this patent
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Abstract
A method and system for operating a computer system in a low power mode in which the central processor unit (CPU) responds only to system events that require CPU operation is described. The invention inclues providing register banks on system logic coupled to the CPU which determines whether interrupt signals generated on the system require CPU attention and the priority to be accorded to the processes associated with the interrupt signals.
Claims15
A system for operating a computer system in a minimal mode, said computer system comprising:
- a CPU having a sleep mode and an awake mode;
- and
- system logic coupled to said CPU, said system logic including a register bank comprising a rising enable register, a falling enable register, a microprocessor register, a promotion register, and a mask register, said microprocessor register being coupled with said mask register such that the contents of said microprocessor and said mask registers are swapped when an interrupt generated on said system is determined to be a high priority process selected from the group consisting of interruptible high priority processes and uninterruptible high priority processes to ensure thereby that said high priority process is not interrupted during its execution by a non-high priority process.
A method for operating a computer system in a minimal power consumption mode comprising the steps of:
- a) coupling a CPU with an ASIC;
- b) receiving an interrupt with said ASIC;
- c) determining that said interrupt is a high priority process selected from a group consisting of interruptible high priority processes and uninterruptible high priority processes;
- and
- d) swapping the contents of a microprocessor register with the contents of a mask register to identify said high priority process and ensure that the execution of said high priority process is not interrupted by non-high priority processes.
2 more elements
A method for operating a computer system in a minimal mode comprising the steps of:
- a) placing a CPU of said computer system in a sleep mode;
- b) setting a mask register to a high or low value;
- c) setting a wake up register to a high or low value;
- d) setting a promotion register to a high or low value;
- e) detecting an interrupt signal using an ASIC coupled to said CPU to detect an edge of an interrupt signal applied to a pin of said ASIC;
- f) processing the interrupt signal, and swapping the value contained in a register on the CPU with the value of said mask register on said ASIC, in response to a determination that said mask register contains a high value;
- g) setting the priority of the interrupt signal to interruptible high priority or uninterruptible high priority wherein
- if the promotion register is set to a high value, then the process associated with the interrupt signal is processed as an uninterruptible high priority process, and
- if the promotion register is set to a low value, then the process associated with the interrupt signal is run as an interruptible high priority process such that the process is executed as an uninterruptible process, but wherein said interruptible process can be interrupted by an uninterruptible process;
- h) waking said CPU, in response to a determination that said wake up register contains a high value;
- and
- i) running the process associated with said processed interrupt signal on said CPU.
9 more elements
A method for operating a computer system in a minimal mode comprising the steps of:
- a) placing a CPU of said computer system in a sleep mode;
- b) setting a mask register to a high or low value;
- c) setting a wake up register to a high or low value;
- d) setting a promotion register to a high or low value;
- e) detecting an interrupt signal using an ASIC coupled to said CPU to detect an edge of an interrupt signal applied to a pin of said ASIC;
- f) processing the interrupt signal, and swapping the value contained in a register on the CPU with the value of said mask register on said ASIC, in response to a determination that said mask register contains a high value;
- g) setting the priority of the interrupt signal to interruptible or uninterruptible wherein
- if the promotion register is set to a high value, then the process associated with the interrupt signal is processed as an uninterruptible high priority process, and
- if the promotion register is set to a low value, then the process associated with the interrupt signal is run as an interruptible high priority process such that the process is executed as an uninterruptible process, but wherein said interruptible high priority process can be interrupted by an uninterruptible high priority process;
- h) waking said CPU, in response to said wake up register and said mask register each containing a high value;
- and
- i) running the process associated with said processed interrupt signal on said CPU.
9 more elements
Dependencies are inferred from the claim text.