DMA emulation via interrupt muxing

A computer system, comprising:

• a memory comprising a plurality of buffers that store data;
• a microprocessor coupled to the memory;
• a memory controller that bridges the memory and the microprocessor to a bus;
• a peripheral device, coupled to the bus, comprising a first and second internal module, wherein the first internal module is a DMA coordinator, a first output line, coupled to the first internal module, that transmit a DMA request signal asserted by the first internal module, a second output line, coupled to the second internal module, that transmit a interrupt signal asserted by the second internal module, an interrupt output circuit, coupled to the first output line and the second output line, that outputs a single interrupt signal on a shared interrupt output line to a microprocessor when the DMA request signal or the interrupt signal is asserted, and an interrupt recording unit, coupled to the first output line and the second output line, that records which of the first and second internal module is an initiator of the single interrupt signal.

A method for managing interrupt signals in a microprocessor, comprising:

• determining a source of an interrupt signal;
• programming and starting a bus master if the source of the interrupt signal is a DMA coordinator module;
• restoring a DMA controller if the source of the interrupt signal is a bus master;
• and
• beginning an interrupt service murine if the interrupt comes from a source other than the DMA coordinator module or a bus master.

A circuit for managing interrupt signals, comprising:

• a interrupt source determinator that determines a source of an interrupt;
• a interrupt service routine initiator that starts an interrupt serve routine in memory when the source of the interrupt is not a DMA coordinator module;
• a bus master programmer, coupled to the interrupt service routine initiator, that sends memory addresses of buffers that are to be accessed by a peripheral to a bus master;
• and
• a DMA controller restorer, coupled to the bus master programmer, that updates a length field counter in a DMA controller to indicate a completed data transfer.