US 5,708,802 AGranted

Semiconductor memory device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsChikayoshi Morishima, Shigeki Ohbayashi

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Abstract

To obtain a semiconductor memory device capable of keeping the internal circuit in active state at all times, without increasing the power consumption during normal operation, and not increasing the number of pins. A burn-in clock generating circuit (1) receives an external clock CLK, a mode signal MODE, and an internal clock INTCLK to output a burn-in clock BICLK to a decoder (5). The burn-in clock BICLK becomes a signal equivalent to the internal clock INTCLK when the mode signal MODE is a fixed signal of H or L indicating normal operation, and becomes a fixed signal of H for indicating activation at all times when the mode signal MODE is a clock at half frequency of the external clock CLK.

Claims10

Dependent claims

A semiconductor memory device comprising:

internal clock generating means for receiving an external clock, and generating an internal clock from said external clock, said internal clock varying between a first level and a second level;
first signal memory means for receiving said external clock and a mode signal, and inputting said mode signal as a first stored data when a predetermined signal change of said external clock occurs;
second signal memory means for receiving said external clock and said first stored data, and inputting said first stored data as a second stored data when said predetermined signal change of said external clock occurs;
signal comparing means for receiving said first and second stored data, and for outputting a comparison result signal after comparing said first stored data and said second stored data;
special clock generating means for receiving said internal clock and said comparison result signal for outputting, based on said comparison result signal, a special clock comprising one of said internal clock and a signal being fixed at said first level;
and
an internal circuit for receiving said special clock, and being in an active state to perform a predetermined action when said special clock is at said first level.

4 more elements

A semiconductor memory device comprising:

internal clock generating means for receiving an external clock to generate an internal clock based on said external clock, said internal clock varying between a first level and a second level;
first to N-th (N.gtoreq.3) signal memory means for commonly receiving said external clock, and respectively storing first to N-th stored data, said first signal memory means for receiving a mode signal and inputting said mode signal as said first stored data when a predetermined signal change of said external clock occurs, wherein an i-th (i=2 to N) signal memory means of said first to N-th signal memory means further receives an (i-1)-th stored data, and inputs said (i-1)-th stored data as the i-th stored data when a predetermined signal change of said external clock occurs;
first to M-th (M.gtoreq.2) signal comparing means each for receiving two consecutive data out of said first to N-th stored data as a first comparative data and a second comparative data, and each for outputting a respective comparison result signal based on comparing said first comparative data and said second comparative data, a combination of said first and second comparative data being different among said first to M-th signal comparing means;
special clock generating means for receiving said internal clock and M comparison result signals outputted from each of said first to M-th signal comparison means, for outputting, a special clock, one of said internal clock and signal being fixed at said first level based on said first to M-th comparison result signals;
and
an internal circuit for receiving said special clock, and being in active state to perform a predetermined action when said special clock is at said first level.

3 more elements

Dependencies are inferred from the claim text.