Asynchronous access system for multiprocessor system and processor module used in the asynchronous access system

A processor module, comprising one of plural processor modules connected to a system bus of a multiprocessor system further having at least one shared memory module connected to the system bus, the processor module including a processor unit and an internal buffer associated with the processor unit, the processor unit issuing access requests, including write access requests, to the shared memory module and writing data into the associated internal buffer, data, written into the associated internal buffer, being read from the associated internal buffer and written into the shared memory module at a respective memory module address via the system bus, said processor module comprising:

• a detector detecting a first predetermined situation, regarding successive data write access requests from the processor module to the shared memory module for storing data at respective write addresses of the shared memory module, as to whether or not the respective, write addresses of the shared memory module for the successive data write access requests are continuous;
• and
• a controller causing the data stored in the associated internal buffer to be written into the shared memory module, automatically and without any instruction from the processor module, when the detector detects, as the first predetermined situation, that the respective, successive write addresses, of a current data write access request and a next preceding write access request, are not continuous.

An asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and a shared memory module connected to the system bus, each processor module issuing requests for access to the shared memory module, the requests including a write access request, to write data of a predetermined number of bits into an area of the shared memory indicated by a respective write address of the shared memory module, and a request for access to the shared memory for other than writing data therein and comprising:

• a processor unit and an internal buffer associated with the processor unit wherein, in each of successive steps, the processor unit writes data of the predetermined number of bits and having a respective write address of the shared memory module, into the associated internal buffer for temporary storage therein;
• a detector detecting a discontinuity, between respective write addresses of the shared memory module of a current write access request and of a next preceding write access request, and issuing a corresponding detection output;
• and
• a controller responding to a detection output of the detector for a current access request of the processor module and causing the data stored in the internal buffer associated with the processor unit to be output over the system bus and written as a block into the area of the shared memory module indicated by the respective write address thereof, automatically and without any instruction from the processor module.

An asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and a shared memory module connected to the system bus, each processor module issuing requests for access to the shared memory module, the requests including access requests to the shared memory module to write data of a predetermined number of bits into an area of the shared memory module indicated by a respective write address of the shared memory module and requests for access to the shared memory module for other than writing data therein and comprising:

• a processor unit and an internal buffer associated with the processor unit, the processor unit writing data of the predetermined number of bits into the respectively associated internal buffer for temporary storage therein, the temporarily stored data to be read from the respectively associated internal buffer and written as a block over the system bus into the shared memory module at a respective write address thereof;
• a detector detecting at least one of plural predetermined conditions and producing a corresponding detection output for each predetermined condition detected thereby, the predetermined conditions comprising:
• (1) a first condition of the occurrence of a write access request, from the processor module to the shared memory module, concurrently with a full condition of the internal buffer,
• (2) a second condition of a discontinuity between successive write addresses of the shared memory module for respective data of successive write access requests from the processor unit to the shared memory module, as between a current write access request and a next preceding write access request of the successive write access requests,
• (3) a third condition of an interval between successive write access requests from the processor unit to the shared memory module exceeding a predetermined time duration, and
• (4) a fourth condition of an access request from the processor unit to the shared memory module which is other than for writing data in the shared memory module;
• and
• a controller responding to a detection output of the detector for a current access request of the processor module and causing the data stored in the internal buffer associated with the processor unit to be output over the system bus and written as a block into the area of the shared memory module indicated by the respective write address thereof, automatically and without any instruction from the processor module.