Virtual memory mapping method and system for address translation mapping of logical memory partitions for BAT and TLB entries in a data processing system

A system for address translation mapping of logical partitions for address translation buffer entries in a data processing system, said system comprising:

• means for receiving a logical address for a memory reference to a selected logical partition among a plurality of logical partitions of a particular block of virtual memory, wherein the block of virtual memory is divided into the plurality of logical partitions, and wherein the logical address includes a plurality of logical partition selection bits selecting the selected logical partition from among the plurality of logical partitions;
• means, responsive to the selected logical partition being valid in real memory, as indicated by a logical partition valid bit associated with the selected logical partition, for compiling a physical address for the memory reference in the selected logical partition from an entry of an address translation buffer that is associated with the particular block of virtual memory regardless of whether logical partitions of said particular block other than said selected logical partition are valid within said real memory, wherein the logical partition valid bit is one of a plurality of logical partitions valid bits contained in the entry associated with the particular block of virtual memory that are each associated with a respective one of the plurality of logical partitions;
• and
• means for retrieving the memory reference within the selected logical partition at the compiled physical address.

A method for address translation mapping of logical partitions for address translation buffer entries in a data processing system, the method comprising the steps of:

• receiving a logical address for a memory reference to a selected logical partition of a particular block of virtual memory, wherein the particular block of virtual memory is divided into a plurality of logical partitions, and wherein a logical address includes a virtual block number addressing the block of memory in virtual memory space, a plurality of logical partition selection bits selecting the selected logical partition within the block of memory, and a real address offset;
• determining if there is a match between the virtual block number of the received logical address and a virtual block number for any entry in an address translation buffer, wherein each entry in the address translation buffer is associated with a block of virtual memory and includes a virtual block number, a real block number addressing the block of memory in real memory, and a plurality of logical partition valid bits, wherein a logical partition of the block of virtual memory is indicated as valid in real memory by an associated logical partition valid bit ›of!among the plurality of logical partition valid bits;
• and
• if there is a match of the virtual block numbers for the received logical address and an entry in the address translation buffer and if the selected logical partition is indicated as valid by the associated logical partition valid bit, combining the real block number with the logical partition selection bits and the real address offset to form a physical address in real memory for the memory reference in the selected logical partition, regardless of whether logical partitions of said particular block other than said selected logical partition are valid within said real memory.

A virtual memory mapping system for translating a logical address for a memory reference to a block of virtual memory into a physical address for the memory reference in real memory, wherein the block of virtual memory is divided into a plurality of logical partitions, and wherein a logical address includes a virtual block number addressing the block of memory in virtual memory space, a plurality of logical partition selection bits selecting the selected logical partition within the block of memory, and a real address offset, the virtual memory mapping system comprising:

• an address translation buffer containing a plurality of entries, wherein each entry in the address translation buffer is associated with a block of virtual memory and includes a virtual block number, a real block number addressing the block of memory in real memory, and a plurality of logical partition valid bits, wherein a logical partition of the block of virtual memory is indicated as valid in real memory by an associated logical partition valid bit among the plurality of logical partition valid bits;
• means for combining the real block number with the logical partition selection bits and the real address offset to form a physical address in real memory for the memory reference in the selected logical partition, when the selected logical partition is indicated as valid by the associated logical partition valid bit;
• a comparator that receives a logical address for a memory reference to a selected logical partition of a block of virtual memory and determines if there is a match between the virtual block number of the received logical address and a virtual block number for any entry in the address translation buffer;
• selection means for selecting the logical partition valid bit associated with the selected logical partition;
• and
• a physical address register that receives and stores the real block number, the logical partition selection bits and the real address offset as a physical address to the real memory for the memory reference, when the logical partition valid bit associated with the selected logical partition indicates the selected partition is valid in real memory regardless of whether logical partitions of said particular block other than said selected logical partition are valid within said real memory.