US 5,708,789 A · Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations

Abstract

According to the present invention, when faulty data bits in a cache memory are not repairable through conventional repair means such as row/column redundancy, the faulty bits are made inaccessible to the microprocessor by rendering invalid an appropriate line of data in the cache memory containing the faulty data. The present invention employs address detection circuitry which detects when a faulty data address stored in the tag RAM is presented during a microprocessor memory cycle and forces the valid bit for that faulty data to a predetermined logic level. When the valid bit associated with the faulty data is set to the predetermined logic level, the tag RAM generates a signal indicative of a "miss" condition. The "miss condition" is communicated to the microprocessor which must access the requested data from main memory, thus effectively bypassing the faulty data. The address detection circuitry of the invalidation circuitry may be expanded to handle any number of faulty data. In this way, a primary or secondary cache memory having faulty data may be utilized.

Claims15

Dependent claims

Circuitry for invalidating faulty data locations in a cache memory, comprising:

a tag RAM which stores a plurality of addresses corresponding to data stored in the cache memory and which has a valid bit input and a match output;
and
invalidation circuitry which invalidates an address of the plurality of addresses corresponding to a faulty bit stored in the cache memory by controlling the value of the valid bit input for the address, such that upon a memory cycle no data stored at the address may be retrieved, wherein the invalidation circuitry further comprises:
a plurality of address detect blocks wherein each address detect block generates an address detect signal if an address unique to the address detect block which corresponds to faulty cache memory data is detected;
a first logic gate which has inputs equal to the address detect signals generated by the address detect blocks and which generates a final address detect signal;
and
a second logic gate which has a first input equal to the final address detect signal and a second input equal to the read/write signal and which generates the valid bit input of the tag RAM.

4 more elements

Dependencies are inferred from the claim text.

Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations

Life of this patent

Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations

Life of this patent

Abstract

Claims15