Method for receiver-side clock recovery for digital signals

A method for receiver-side clock recovery for digital signals having a constant bit rate following cell-structured, asynchronous transmission, the method comprising the steps of:

• initially reading digital signals into a FIFO memory with a received clock until the memory is filled to a predetermined level;
• reading out the digital signals stored in the FIFO memory with a readout clock whose frequency is lower than the frequency of the received clock;
• generating daring readout a signal for controlling the frequency of the readout clock, the readout clock frequency derived from a loading state of the FIFO memory;
• and
• forming an average value of the loading state of the FIFO memory through a number of queries of the loading state of the FIFO memory.

A digital signal transmission system comprising:

• a memory for reading a received clock and digital signals having a constant bit rate following cell-structured, asynchronous transmission;
• a signal averager receiving an input from the memory, the signal averager for averaging multiple values of a loading state of the memory;
• a clock generator receiving an input from the signal averager, the clock generator receiving an input from the signal averager;
• and
• a central clock providing timing signals to the memory, signal averager, and clock generator
• the memory being a FIFO memory.