Frame synchronous signal detector

A frame synchronous signal detector, comprising:

• a parallel converter which sequentially receives units of parallel data according to a clock, each of said units of parallel data having a first predetermined number of bits, produces combination data by combining the units of parallel data associated with two consecutive pulses of the clock, wherein a first of the combination data produced by said parallel converter is associated with a present pulse of the clock and a next-previous pulse of the clock, a second of the combination data is associated with the next-previous pulse of the clock and a second-to-next-previous of the clock, and a third of the combination data is associated with two consecutive pulses of the clock situated a predetermined number of pulses of the clock previous to the present clock pulse, supplies the first of the combination and the second of the combination data as control data and supplies the third of the combination data as middle data;
• a detector part which receives said first combination data and said second combination data which have been supplied from said parallel converter as the control data, respectively divides said first combination data and said second combination data into a first plurality of predetermined segments, each of the first plurality of predetermined segments being displaced by one bit, in a direction of a least significant bit of said combination data, from a next-previous one of the first plurality of predetermined segments, thereby producing respective divided combination data, compares the respective divided combination data with a value of a frame synchronous signal which has previously been mapped and produces a first comparison result, and outputs a starting signal and a selection signal corresponding to the respective divided combination data which has been determined according to the first comparison result;
• and
• a buffer which divides the middle data supplied from said parallel converter into a second plurality of predetermined segments, each of the second plurality of predetermined segments being displaced by one bit, in a direction of a least significant bit of said middle data, from a next-previous one of the second plurality of predetermined segments, thereby producing respective divided middle data, receives a selection signal of said detector corresponding to the respective divided data of the middle data, and outputs the divided data corresponding to the selection signal.