Voltage level detector

A voltage level detector including a first detector section having first and second transistors connected in series, a second detector section having third and fourth transistors connected in series, the first and second detector sections being arranged in parallel and connected to a power supply via a resistor, said voltage level detector comprising:

• a control terminal of said second transistor being supplied with a target signal whose voltage level is to be detected;
• a first delay circuit, connected to a control terminal of said first transistor, for inverting the level of said target signal and for allowing the inverted target signal to be supplied to said first transistor at a time later than the input of said target signal to said second transistor;
• a second delay circuit, connected to a control terminal of said third transistor, for allowing said target signal to be supplied to said third transistor at a time later than the input of the inverted target signal to said first transistor via said first delay circuit;
• and
• a third delay circuit, connected to a control terminal of said fourth transistor, for inverting the level of said target signal and for allowing the inverted target signal to be supplied to said fourth transistor at a time later than the input of the target signal to said second transistor and earlier than the input of the inverted target signal to said first transistor via said first delay circuit.