Method and structure for controlling internal operations of a DRAM array

A method of operating a dynamic random access memory (DRAM) array in response to a clock signal and an access control signal, the method comprising the steps of:

• applying the clock signal and the access control signal to a synchronous state machine, wherein the synchronous state machine enters a first state and a second state in response to the clock signal when the access control signal is asserted;
• initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating a sense amplifier equalization circuit of the DRAM array when the state machine enters said first state for a first time;
• and
• initiating a sense amplifier enabling operation when the state machine enters said second state.

A control circuit for controlling a dynamic random access memory (DRAM) array having a plurality of bit line equalization circuits, a plurality of sense amplifiers, and a plurality of sense amplifier equalization circuits, the control circuit comprising:

• a clock input terminal for receiving a clock signal having a first state and a second state;
• an access control signal terminal for receiving an access control signal;
• a first signal generation circuit which generates an equalization signal when the access control signal is asserted and the clock signal undergoes a first transition, wherein the equalization signal disables the bit line equalization circuits and the sense amplifier equalization circuits;
• and
• a second signal generation circuit which generates a sense amplifier control signal when the access control signal is asserted and the clock signal undergoes a second transition, wherein the sense amplifier control signal enables the sense amplifiers.

A method of operating a dynamic random access memory (DRAM) array, comprising the steps of:

• (a) providing a clock signal which transitions between a first state and a second state;
• (b) providing an access control signal, wherein the access control signal is asserted to initiate an access to the DRAM array;
• (c) initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating sense amplifier equalization circuit of the DRAM array when the access control signal is asserted and the clock signal undergoes a first transition;
• (d) initiating a sense amplifier enabling operation when the access control signal is asserted and the clock signal undergoes a second transition;
• (e) initiating a column address decoding operation when the access control signal is asserted and the clock signal undergoes a third transition;
• (f) providing a test signal having a first state and a second state;
• (g) performing steps (a)-(e) when the test signal is in the first state;
• and
• (h) initiating the row address decoding operation, deactivating the bit line equalization circuit, deactivating the sense amplifier equalization circuit, enabling the sense amplifier, and enabling the column address decoding operation in a self-timed manner, independent of the clock signal, when the test signal is in the second state.

A method of operating a dynamic random access memory (DRAM) array, comprising the steps of:

• (a) providing a clock signal which transitions between a first state and a second state;
• (b) providing an access control signal, wherein the access control signal is asserted to initiate an access to the DRAM array;
• (c) initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating sense amplifier equalization circuit of the DRAM array when the access control signal is asserted and the clock signal undergoes a first transition;
• (d) initiating a sense amplifier enabling operation when the access control signal is asserted and the clock signal undergoes a second transition;
• (e) initiating a column address decoding operation when a second access control signal is asserted and the clock signal undergoes a third transition;
• (f) providing a test signal having a first state and a second state;
• (g) performing steps (a)-(e) when the test signal is in the first state;
• and
• (h) initiating the row address decoding operation, deactivating the bit line equalization circuit, deactivating the sense amplifier equalization circuit, enabling the sense amplifier, and enabling the column address decoding operation in a self-timed manner, independent of the clock signal, when the test signal is in the second state.