Semiconductor memory decoder device

Abstract

A memory device comprising a cell array including first and second cell array blocks for storing data therein, a first row address buffer for generating a first internal row address signal in response to an external row address signal and a first row address strobe signal, a second row address buffer for generating a second internal row address signal in response to the external row address signal and a second row address strobe signal, a first pre-decoder for pre-decoding the first internal row address signal from the first row address buffer, a second pre-decoder for pre-decoding the second internal row address signal from the second row address buffer, a first row decoder for selectively driving word lines in the first cell array block in response to the pre-decoded first internal row address signal from the first pre-decoder, and a second row decoder for selectively driving word lines in the second cell array block in response to the pre-decoded second internal row address signal from the second pre-decoder. The memory device further comprises a row address strobe bar buffer for generating the first and second row address strobe signals in response to an external row address strobe bar signal, a column address strobe bar signal, a write enable signal, an output enable signal and a mode enable signal.

Dependencies are inferred from the claim text.