Clock synchronous semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array having a plurality of memory cells;
• a first data register for temporarily holding data of a plurality of memory cells selected at a time in said memory cell array;
• a second data register receiving and storing data held by said first data register;
• detection means coupled to receive an operation mode instructing signal indicating that said second data register is accessed when active, for detecting that said second data register is under a non-accessed state in response to inactivation of said operation mode instruction signal;
• and
• transfer means responsive to detection of non-accessing to said second data register by said detection means and a data transfer instruction signal for conducting data transfer from said first data register to said second data register, said transfer means including means responsive to said detection means detecting that said operation mode instruction signal is active for stopping said data transfer.