Memory device having a plurality of bitlines between adjacent columns of sub-wordline drivers

Abstract

A memory device of the present invention includes a plurality of bitlines and main wordlines formed in first and second directions, respectively, to form a matrix, and a plurality of memory cells coupled to each bitline. A first decoder decodes first address signals and provides first decoded signals to the plurality of main wordlines. A second decoder decodes second address signals and provides second decoded signals. The memory device also includes n-th number of groups of drivers, and each group has a plurality of sub-drivers formed in a third direction to receive a corresponding second decoded signal. Each sub-driver has a plurality of selection lines coupled to corresponding memory cells, and a plurality of sense amplifiers is coupled to said plurality of bitlines, wherein more than two bitlines are formed between adjacent groups of drivers.

Dependencies are inferred from the claim text.