Multiport field memory

A multiport field memory comprising:

• a cell array having memory cells arranged in rows and columns;
• a plurality of bit line pairs for transferring data from and to the memory cells;
• gate transmission means connected to the plurality of bit line pairs, said gate transmission means including
• a plurality of data line pairs, each data line pair having a first data line and a second data line, the first data lines of the plurality of data line pairs being directly connected together, and the second data lines of the plurality of data line pairs being directly connected together;
• a plurality of first transfer gate pairs, each first transfer gate pair being connected between one of the bit line pairs and one of the data line pairs;
• and
• a plurality of second transfer gate pairs, each second transfer gate pair being connected to one of the data line pairs;
• a plurality of ports, each port including register means for storing data, and each port being connected to one of the second transfer gate pairs;
• and
• data cross-transmission control means including
• first gate control means for transferring first gate drive control signals to the first transfer gate pairs in order to activate at least one of the first transfer gate pairs to couple the bit line pairs connected to the activated first transfer gate pairs to the data line pairs also connected to the activated first transfer gate pairs;
• and
• second gate control means for transferring second gate drive control signals to the second transfer gate pairs in order to activate one of the second transfer gate pairs to couple the register means in the port that is connected to the activated second transfer gate pair to all of the data line pairs,
• wherein the data cross-transmission control means operates to allow data to be transferred from any one of the ports through the corresponding second transfer gate pair and through any of the first transfer gate pairs to any of the bit line pairs.