Regressive drive sense amplifier

A pull-down circuit in a sense amplifier having a common node and receiving a power Supply voltage, the pull-down circuit comprising:

• a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground;
• a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor;
• a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage;
• a first-stage transistor tree including:
• a first N-channel transistor having a source coupled to ground, a gate, and a drain coupled to the gate and to a first node, and
• a first resistive element coupled between the power supply and the first node;
• and
• a second-stage transistor tree stage including:
• a first P-channel transistor having a source coupled to the power supply, a gate, and a drain coupled to the gate, and
• a second P-channel transistor having a source coupled to the gate and drain of the first p-channel transistor, a gate coupled to the first node, and a drain coupled to coupled to the gate of the choke transistor, and
• a second resistive element coupled between ground and the drain of the second P-channel transistor.

A method of discharging a sense amplifier having a common node and receiving a power supply voltage, the method comprising the steps of:

• providing an input signal;
• providing a bias voltage based on the value of the power supply voltage, wherein a relatively low bias voltage is provided at relatively low power supply voltages and a relatively high bias voltage is provided at relatively high power supply voltages;
• regulating an input current based on the power supply voltage and the bias voltage to increase the input current at relatively low bias voltages and to decrease the input current at relatively high bias voltages;
• and
• discharging the sense amplifier based on the input signal and the input current.

A method of controlling a pull-down circuit in a sense amplifier having a common node and receiving a power supply voltage, the pull-down circuit including a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground;

• a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor;
• and a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage, the method comprising the steps of:
• providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor;
• and
• providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

A sense amplifier comprising:

• a common node shared with other sense amplifiers;
• a pair of sense amplifier transistors having a cross-coupled gate and drain configuration to sense charge in a memory array and having sources coupled together and coupled to the common node;
• a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground;
• a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor;
• a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage;
• and
• a regressive drive bias circuit coupled to the gate of the choke transistor and providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor, and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

A memory integrated circuit comprising:

• a memory array;
• a common node;
• a pair of sense amplifier transistors having a cross-coupled gate and drain configuration to sense charge in the memory array and having sources coupled together and coupled to the common node;
• a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground;
• a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor;
• a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage;
• and
• a regressive drive bias circuit coupled to the gate of the choke transistor and providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor, and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.