Low noise sense amplifier control circuits for dynamic random access memories and related methods

A method for generating a sense amplifier drive signal on a sense amplifier drive node of a sense amplifier in an integrated circuit memory device including a pair of bit lines, a memory cell connected to one of the bit lines, and a sense amplifier connected between the pair of bit lines wherein the sense amplifier detects and amplifies a difference between voltages of the bit lines responsive to the sense amplifier drive signal, said method comprising the steps of:

• generating a comparison signal in response to a comparison of the sense amplifier drive signal and a predetermined reference signal, and in response to an enable signal;
• generating a gating signal at a gate node in response to the comparison signal and in response to a magnitude of the sense amplifier drive signal so that the gating signal has a first magnitude when the sense amplifier drive signal is below a predetermined threshold and a second magnitude when the sense amplifier drive signal is above the predetermined threshold;
• and
• providing electrical energy to said sense amplifier drive node responsive to the gating signal so that electrical energy is provided at a first rate when the gating signal has the first magnitude and electrical energy is provided at a second rate when the gating signal has the second magnitude thereby generating the sense amplifier drive signal.

A method according to claim 11 wherein said step of generating said gating signal on said gate node comprises the steps of:

• providing an electrical connection between a power voltage and said gate node so that said gating signal has a third magnitude in response to an absence of said trigger signal so that electrical energy is not provided to said sense amplifier drive node;
• providing an electrical connection from said gate node to a ground voltage through a load circuit in response to said trigger signal when the sense amplifier control signal is below the predetermined threshold;
• and
• providing an electrical connection from said gate node to the ground voltage through a by-pass circuit in response to the trigger signal when the sense amplifier control signal is above the predetermined threshold.

A sense amplifier control circuit for an integrated circuit memory device having a pair of bit lines, a memory cell connected to one of the bit lines, and a sense amplifier connected between the pair of bit lines for detecting and amplifying a difference in voltages of the pair of bit lines according to a sense amplifier drive signal on a sense amplifier input node, said sense amplifier control circuit comprising:

• trigger means for comparing the sense amplifier drive signal with a predetermined reference voltage in response to a sense enable signal, and for generating a trigger signal in response to said comparison;
• sense amplifier drive control means for generating a gate signal at a gate node in response to said trigger signal, so that said gate signal has a first magnitude when the sense amplifier drive signal is below a predetermined threshold and a second magnitude when the sense amplifier drive signal is above the predetermined threshold;
• and
• sense amplifier drive means for receiving a power voltage and generating the sense amplifier drive signal on the sense amplifier input node in response to the gate signal at said gate node.

A sense amplifier control circuit for an integrated circuit memory device having a pair of bit lines, a memory cell connected to one of the bit lines, an N sense amplifier connected between the pair of bit lines for detecting and amplifying a difference in the voltages of the pair of bit lines according to a first sense amplifier driving signal, and a P sense amplifier connected between the pair of bit lines for detecting and amplifying the difference in voltages of the pair of bit lines responsive to a restore voltage and for restoring a charge of the memory cell, said sense amplifier control circuit comprising:

• trigger means for comparing the restore voltage with a predetermined reference voltage in response to a sense enable signal, and for generating a trigger signal in response to said comparison;
• P sense amplifier drive control means for generating a gate voltage at a gate node in response to said trigger signal, so that said gate voltage has a first magnitude when the sense amplifier drive signal is below a predetermined threshold and a second magnitude when the sense amplifier drive signal is above the predetermined threshold;
• and
• P sense amplifier drive means for receiving a power voltage and generating the sense amplifier drive signal on the P sense amplifier input node in response to the gate voltage at said gate node.

An integrated circuit memory device comprising:

• a pair of bit lines;
• a memory cell connected to one of said bit lines;
• a sense amplifier control circuit which generates a sense amplifier drive signal on a sense amplifier drive node responsive to an enable signal, wherein said sense amplifier control circuit comprises,
• a drive circuit which generates a gating signal in response to a comparison of the sense amplifier drive signal and a predetermined reference signal and in response to a magnitude of the sense amplifier drive signal so that the gating signal has a first magnitude when the sense amplifier drive signal is below a predetermined threshold and a second magnitude when the sense amplifier drive signal is above the predetermined threshold, and
• a driver which provides electrical energy to said sense amplifier drive node responsive to the gating signal thereby generating the sense amplifier drive signal;
• and
• a sense amplifier connected between said pair of bit lines, wherein said sense amplifier detects and amplifies a difference between voltages of said bit lines responsive to the sense amplifier drive signal on said sense amplifier drive node.