Semiconductor memory device with reduced current consumption during precharge and reading periods

A semiconductor memory device comprising:

• a plurality of memory cells;
• a control signal generator providing at least a bit line selection signal and a read control voltage;
• a plurality of bit lines each connected to at least one of said plurality of memory cells;
• a bit line selecting circuit connected between said plurality of bit lines and a connection node and having an input receiving said bit line selection signal from said control signal generator for controlling the selection of one of said plurality of bit lines as a selected bit line to establish an electrical connection between said selected bit line and said connection node during at least a precharge period and a read period;
• a precharge circuit supplying a precharge voltage to said connection node;
• an output circuit providing an output signal in response to a signal at said connection node from a memory cell which occurs simultaneously with the read control voltage from the control signal generator being supplied to a control input of the output circuit;
• and
• wherein said precharge circuit includes at least a first transistor having a first electrode receiving said precharge voltage, a second electrode connected to said connection node, and a control electrode connected to a control terminal for receiving a fixed voltage that ensures that the first transistor is biased to be normally conductive.