Data output control circuit of semiconductor memory device having pipeline structure

A method of testing a semiconductor memory device having a pipeline structure, comprising the steps of:

• storing same data in a plurality of memory cells;
• reading out the data from the plurality of memory cells to produce data signals and amplifying the data signals;
• determining whether all said data signals are same, to generate a determination result signal;
• selectively transferring one of signals associated with said amplified data signals and predetermined signals in accordance with said determination result signal in synchronous with a synchronous signal;
• providing, as an indication signal, one of a low level signal, a high level signal and a signal indicative of a high impedance state in response to each of the transferred signals;
• and
• judging whether the plurality of memory cells are correctly operable, using at least one of the indication signals.

A data output control circuit comprising:

• a plurality of data amplifiers receiving a plurality of data signals;
• a comparing circuit determining that all said data signals are same and outputting a determination signal indicating a coincidence or a non-coincidence;
• a synchronous signal generator generating a synchronous signal;
• a first synchronizing circuit and a plurality of second synchronizing circuits being commonly supplied with said synchronous signal, said first synchronizing circuit transferring said determination signal at timing of generating of said synchronous signal, said plurality of second synchronizing circuits transferring said plurality of data signals at timing of generating of said synchronous signal;
• and
• a plurality of output circuits receiving said determination signal from said first synchronizing circuit and said data signals from said second synchronizing circuits and outputting said plurality of data signals in response to said determination signal.