High performance redundancy in an integrated memory system

A memory system for use in computer systems, the memory system comprising:

• a) a bit redundancy steering mechanism for controlling which bits in said memory system are to be replaced by redundant bits, said bit redundancy steering mechanism having an address signal input and a timing signal input;
• b) a memory data array, said data array having a plurality of address signal inputs and a timing signal input;
• c) a first timing signal path, said first timing signal path conducting a timing signal to said timing signal input of said bit redundancy steering mechanism;
• d) a second timing signal path, said second timing signal path conducting said timing signal to said timing signal input of said memory data array, and wherein said second timing signal path has a propagation delay longer than said first timing signal path;
• e) a plurality of address paths, said plurality of address paths conducting a plurality of address signals to said plurality of address signal inputs of said memory data array;
• f) a bit redundancy address signal path, said bit redundancy address signal path conducting at least one of said plurality of address signals to said bit redundancy steering mechanism, and wherein said bit redundancy address signal path has a propagation delay shorter than said plurality of address paths.