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US 5,708,611 AGranted
Synchronous semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHisashi Iwamoto, Yasuhiro Konishi
Life of this patent
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Abstract
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.
Claims5
A synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring said internal clock signal, comprising:
- a plurality of memory arrays including a plurality of memory cells arranged in a matrix,
- an internal clock generation circuit for generating said internal clock signal in synchronization with an external clock signal,
- a data input/output circuit for carrying out data input and output between a selected memory cell in said plurality of memory arrays and an external source in synchronization with said internal clock signal, and
- a control circuit for inactivating said internal clock generation circuit for a predetermined time period in response to designation of said mode not requiring said internal clock signal.
1 more element
Dependencies are inferred from the claim text.